A 5.9pJ/b 10Gb/s serial link with unequalized MM-CDR in 14nm tri-gate CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 58, Issue , 2015, Pages 184-185

  Dokania, Rajeev ^a   Kern, Alexandra ^a   He, Mike ^a   Faust, Adam ^a   Tseng, Richard ^a   Weaver, Skyler ^a   Yu, Kai ^a   Bil, Christiaan ^a   Liang, Tao ^a   O'Mahony, Frank ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK AND DATA RECOVERY CIRCUITS (CDR CIRCUITS);

ANALOG FUNCTIONS; CHANNEL CHARACTERISTICS; HIGH SPEED SERIAL LINKS; MAINTAINING LINK; MODERN MICROPROCESSOR; OPTIMIZED PROCESS; POWER REDUCTIONS; TECHNOLOGY SCALING;

CMOS INTEGRATED CIRCUITS;

EID: 84940777614     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2015.7062987     Document Type: Conference Paper

References (5)

1. F. Spagna, et al., "A 78mW 11.8Gb/s Serial Link Transceiver with Adaptive RX Equalization and Baud-Rate CDR in 32nm CMOS, " ISSCC Dig. Tech. Papers, pp. 366-367, Feb. 2010
2. J. F. Bulzacchelli, et al., "A 78mW 11.1Gb/s 5-Tap DFE Receiver with Digitally Calibrated Current-Integrating Summers in 65nm CMOS, " ISSCC Dig. Tech. Papers, pp. 368-369, Feb. 2009
3. S. Quan, et al., "A 1.0625-to-14.025Gb/s Multimedia Transceiver with Full-rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40nm CMOS, " ISSCC Dig. Tech. Papers, pp. 348-349, Feb. 2011
4. M. Ramezani, et al., "An 8.4mW/Gb/s 4-Lane 48Gb/s Multi-Standard-Compliant Transceiver in 40nm Digital CMOS Technology, " ISSCC Dig. Tech. Papers, pp. 352-353, Feb. 2011
5. J. Savoj, et al., "A Wide Common-Mode Fully-Adaptive Multi-Standard 12.5Gb/s Backplane Transceiver in 28nm CMOS, " IEEE Symp. VLSI Circuits, pp. 104-105, 2012