A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2012, Pages 104-105

  Savoj, Jafar ^a   Hsieh, Kenny ^a   Upadhyaya, Parag ^a   An, Fu Tai ^a   Bekele, Ade ^a   Chen, Stanley ^a   Jiang, Xuewen ^a   Lai, Kang Wei ^a   Poon, Chi Fung ^a   Sewani, Aman ^a   Turker, Didem ^a   Venna, Karthik ^a   Wu, Daniel ^a   Xu, Bruce ^a   Alon, Elad ^b   Chang, Ken ^a  

^a XILINX INC   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BACKPLANE TRANSCEIVER; BACKPLANES; COMMONMODE; FREQUENCY BOOST; ISI CANCELLATION; LMS ALGORITHMS; MULTI-STANDARD; RING OSCILLATOR; WIDE-BAND;

CLOCKS; VLSI CIRCUITS;

TRANSCEIVERS;

EID: 84866601827     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2012.6243811     Document Type: Conference Paper

References (3)

1. F. Zhong, et. al., "A 1.0625-14.025Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating Tap Decision-Feedback Equalizer in 40nm CMOS," IEEE JSSC, vol. 46, no. 12, pp. 3126-312.59, Dec. 2011.
2. A. K. Joy, et. al., "Analog-DFE-Based 16Gb/s SerDes in 40nm CMOS That Operates Across 34dB Loss Channels at Nyquist with a Baud Rate CDR and 1.2Vpp Voltage-Mode Driver," ISSCC Dig. Tech. Papers, pp. 350-351, Feb. 2011.
3. K. Chang, et. al., "An 8Gb/s/link, 6.5mW/Gb/s Memory Interface with Bimodal Request Bus," IEEE ASSCC, pp. 21-24, Nov. 2009.