An 8.4mW/Gb/s 4-lane 48Gb/s multi-standard-compliant transceiver in 40nm digital CMOS technology

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 352-353

  Ramezani, Mehrdad ^a   Abdalla, Mohamed ^a   Shoval, Ayal ^a   Van Ierssel, Marcus ^a   Rezayee, Afshin ^b   McLaren, Angus ^a   Holdenried, Chris ^a   Pham, Jennifer ^a   So, Eric ^a   Cassan, David ^a   Sadr, Saman ^a  

^a Snowbush Gennum   (Canada)

^b SecureKey   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CONTINUOUS TIME SYSTEMS; INTEGRATED CIRCUIT DESIGN; TRANSCEIVERS;

BANDWIDTH LIMITATION; CLOCK GENERATION; CONTINUOUS TIME LINEAR EQUALIZER (CTLE); DIGITAL CMOS TECHNOLOGY; DIGITAL PROGRAMMABILITY; FREQUENCY TUNING RANGE; RING OSCILLATOR; SUPPLY VOLTAGES;

CMOS INTEGRATED CIRCUITS;

EID: 79955739193     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746350     Document Type: Conference Paper

References (3)

1. Ganesh Balamurugan, Frank O'Mahony, Mozhgan Mansuri, James E Jaussi, Joseph T Kennedy, Bryan Casper, "A 5-to-25Gb/s 1.6-to-3.8mW/(Gb/s) Reconfigurable Transceiver in 45nm CMOS", IEEE Solid-State Circuits Conference, pp. 372-373, Feb. 2010.
2. Nagendra Krishnapura, Majid Barazande-Pour, Qasim Chaudhry,John Khoury, Kadaba Lakshmikumar, Akshay Aggarwal , "A 5Gb/s NRZ Transceiver with Adaptive Equalization for Backplane Transmission", IEEE Solid-State Circuits Conference, pp.60-61, Feb. 2005.
3. Hidaka, Y. Weixin Gai Horie, T. Jian Hong Jiang Koyanagi, Y. Osone, H., "A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control", IEEE J. Solid-State Circuits, vol. 44, pp. 3547-3559, Dec. 2009.