A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 366-367

  Spagna, Fulvio ^a   Chen, Lidong ^a   Deshpande, Mamatha ^a   Fan, Yongping ^a   Gambetta, Doug ^a   Gowder, Sujatha ^a   Iyer, Sitaraman ^a   Kumar, Rohit ^a   Kwok, Peter ^a   Krishnamurthy, Renuka ^a   Lin, Chien Chun ^a   Mohanavelu, Ravindran ^a   Nicholson, Roan ^a   Ou, Jeff ^a   Pasquarella, Marcus ^a   Prasad, Kavitha ^a   Rustam, Hendra ^a   Tong, Luke ^a   Tran, Amanda ^a   Wu, John ^a   Zhang, Xuguang ^a   more..

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE EQUALIZER; BAUD RATE; CHANNEL LOSS; COMPLEX EQUALIZATION; CROSSTALK EFFECT; DATA RATES; IMPEDANCE DISCONTINUITIES; IO PORTS; POWER BUDGETS; SERIAL-LINK TRANSCEIVER;

MICROPROCESSOR CHIPS;

BIT ERROR RATE;

EID: 77952190393     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433823     Document Type: Conference Paper

References (7)

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2. P. S.R. Diniz, Adaptive Filtering: Algorithms and Practical Implementations, Third Edition, Springer, 2000.
3. J. Bulzacchelli, et al., "A 78mW 11.1Gb/s 5-Tap DFE Receiver with Digitally Calibrated Current-Integrating Summers in 65nm CMOS," ISSCC Dig. Tech. Papers, pp. 368-369, Feb., 2009.
4. M. Pozzuoli, et al., "A Multi-Standard 1.5 to 10Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication," IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1306-1314, April, 2009.
5. K. H. Mueller and M. Muller, "Timing recovery in digital synchronous data receivers," IEEE Trans. Communications, vol. COM-24, no. 5, p. 516-531, May, 1976.
6. V. Balan, et al., "A 4.8-6.4-Gb/s Serial Link for Backplane Applications Using Decision Feedback Equalization," IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1957-1967, Sept., 2006.
7. M. Harwood, et al., "A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery," ISSCC Dig. Tech. Papers, pp. 436-437, Feb., 2007.