A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 58, Issue , 2015, Pages 310-311

  Karl, Eric ^a   Guo, Zheng ^a   Conary, James W ^a   Miller, Jeffrey L ^a   Ng, Yong Gee ^a   Nalam, Satyanand ^a   Kim, Daeyeon ^a   Keane, John ^a   Bhattacharya, Uddalak ^a   Zhang, Kevin ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FINFET; LOGIC DESIGN; LOW POWER ELECTRONICS; PROGRAMMABLE LOGIC CONTROLLERS; STATIC RANDOM ACCESS STORAGE; SYSTEM-ON-CHIP; THRESHOLD VOLTAGE; VOLTAGE SCALING;

LEAKAGE CONSTRAINTS; LOW-POWER OPERATION; MINIMUM OPERATING VOLTAGES (VMIN); SHORT-CHANNEL EFFECT; SUBTHRESHOLD SLOPE; SUPPLY-VOLTAGE SCALING; SYSTEM-ON-A-CHIP DESIGNS; TECHNOLOGY AND DESIGNS;

INTEGRATED CIRCUIT DESIGN;

EID: 84940768132     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2015.7063050     Document Type: Conference Paper

References (6)

1. E. Karl et al., "A 4.6GHz 162Mb SRAM Design in 22nm Tri-Gate CMOS Technology with Integrated Active VMIN-Enhancing Assist Circuitry", ISSCC Dig. Tech. Papers, pp. 230-231, Feb. 2012.
2. S. Natarajan et al., "A 14nm Logic Technology Featuring 2nd-Generation FinFET Transistors, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588um2 SRAM cell size", IEDM Dig. Tech. Papers, in press, 2014.
3. T. Song et al., "A 14nm FinFET 128Mb 6T SRAM with Vmin-Enhancement Techniques for Low-Power Applications", ISSCC Dig. Tech. Papers, pp. 232-233, Feb. 2014.
4. Y.-H. Chen et al., "A 16nm 128Mb SRAM in High-K Metal-Gate FinFET Technology with Write-Assist Circuitry for Low-Vmin Applications", ISSCC Dig. Tech. Papers, pp. 238-239, Feb. 2014.
5. H. Pilo et al., "A 64Mb SRAM in 22nm SOI Technology Featuring Fine-Granularity Power Gating and Low-Energy Power-Supply Partition Techniques for 37% Leakage Reduction", ISSCC Dig. Tech. Papers, pp. 322-323, Feb. 2013.
6. K.-I. Seo et al., "A 10nm Platform Technology for Low Power and High Performance Application Featuring FINFET Devices with Multi Workfunction Gate Stack on Bulk and SOI", VLSI Tech. Dig. Tech. Papers, pp. 12-13, 2014.