A 16nm 128Mb SRAM in high-? metal-gate FinFET technology with write-assist circuitry for low-VMIN applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 57, Issue , 2014, Pages 238-239

  Chen, Yen Huei ^a   Chan, Wei Min ^a   Wu, Wei Cheng ^a   Liao, Hung Jen ^a   Pan, Kuo Hua ^a   Liaw, Jhon Jhy ^a   Chung, Tang Hsuan ^a   Li, Quincy ^a   Chang, George H ^a   Lin, Chih Yung ^a   Chiang, Mu Chi ^a   Wu, Shien Yang ^a   Natarajan, Sreedhar ^a   Chang, Jonathan ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUITS; MOLECULAR BIOLOGY; STATIC RANDOM ACCESS STORAGE; TECHNOLOGY;

BETTER PERFORMANCE; CONVENTIONAL TECHNIQUES; DEVICE VARIATIONS; OPERATING REGIONS; PROCESS VARIATION; RANDOM DOPANT FLUCTUATION; SHORT-CHANNEL EFFECT; TECHNOLOGY SOLUTIONS;

TRANSISTORS;

EID: 84898062752     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2014.6757416     Document Type: Conference Paper

References (5)

1. Y. Wang et al., "Dynamic Behavior of SRAM Data Retention and a Novel Transient Voltage Collapse technique for 0.6V 32nm LP SRAM", IEDM Dig. Tech. Papers, Dec. 2011, pp 32.1.1-32.1.4.
2. 2 Cell in 32nm High-K Metal-Gate CMOS", ISSCC Digest of Technical Papers, Feb. 2010, pp 348-349.
3. H. Pilo et al., "A 64Mb SRAM in 32nm High-k Metal Gate SOI Technology with 0.7V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements," ISSCC Digest of Technical Papers, Feb. 2011, pp 254-256.
4. Eric Karl et al., "A 4.6GHz 162Mb SRAM Design in 22nm Tri-Gate CMOS Technology with Integrated Active Vmin Enhanced Assist Circuitry," ISSCC Digest of Technical Papers, Feb. 2012, pp 230-231.
5. Jonathan Chang et al., "A 20nm 112Mb SRAM in High-k Metal-Gate with Assist Circuitry for Low-Leakage and Low-Vmin Applications" ISSCC Digest of Technical Papers, Feb. 2013, pp 316-317.