A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2014, Pages

  Seo, K I ^c   Haran, B ^b   Gupta, D ^b   Guo, D ^b   Standaert, T ^b   Xie, R ^b   Shang, H ^b   Alptekin, E ^b   Bae, D I ^c   Bae, G ^c   Boye, C ^b   Cai, H ^b   Chanemougame, D ^d   Chao, R ^b   Cheng, K ^b   Cho, J ^b   Choi, K ^b   Hamieh, B ^d   Hong, J G ^c   Hook, T ^b   Jang, L ^b   Jung, J ^c   Jung, R ^b   Lee, D ^c   Lherron, B ^d   Kambhampati, R ^b   Kim, B ^c   Kim, H ^b   Kim, K ^c   Kim, T S ^c   Ko, S B ^b   Lie, F L ^b   Liu, D ^b   Mallela, H ^b   McLellan, E ^b   Mehta, S ^b   Montanini, P ^d   Mottura, M ^d   Nam, J ^b   Nam, S ^b   Nelson, F ^b   Ok, I ^b   Park, C ^b   Park, Y ^c   Paul, A ^b   Prindle, C ^b   Ramachandran, R ^b   Sankarapandian, M ^b   Sardesai, V ^b   Scholze, A ^b   Seo, S C ^b   Shearer, J ^b   Southwick, R ^b   Sreenivasa, R ^a   Stieg, S ^b   Strane, J ^b   Sun, X ^b   Sung, M G ^b   Surisetty, C ^b   Tsutsui, G ^b   Tripathi, N ^b   Vega, R ^b   Waskiewicz, C ^b   Weybright, M ^b   Yeh, C C ^b   Bu, H ^b   Burns, S ^b   Canaperi, D ^b   Celik, M ^d   Colburn, M ^b   Jagannathan, H ^b   Kanakasabaphthy, S ^b   Kleemeier, W ^d   Liebmann, L ^b   McHerron, D ^b   Oldiges, P ^b   Paruchuri, V ^b   Spooner, T ^b   Stathis, J ^b   Divakaruni, R ^b   Gow, T ^b   Iacoponi, J ^b   Jenq, J ^e   Sampson, R ^d   Khare, M ^b   more..

^a State University of New York   (United States)

^b IBM MICROELECTRONICS   (United States)

^c SAMSUNG Electronics   (South Korea)

^d STMICROELECTRONICS   (France)

^e UMC   (China)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC GATES;

BULK AND SOI SUBSTRATES; FINFET DEVICES; HIGH PERFORMANCE APPLICATIONS; MULTI PATTERNING; OPTICAL PATTERNING; PLATFORM TECHNOLOGY; SELF ALIGNED PROCESS; STATIC NOISE MARGIN;

FINFET;

EID: 84907688609     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2014.6894342     Document Type: Conference Paper

References (6)

1. H.-J. Cho et al., IEDM, pp. 3350-3353, 2011
2. H. Shang et al., VLSI, pp 129-130, 2012
3. C. Auth et al., VLSI, pp 131-132, 2012
4. S. Wu et al., IEDM, pp 254-257, 2013
5. J. Yuan et al., ICSICT, pp 1130-1133, 2008
6. X. Chen et al., VLSI, pp88-89, 2008