A 16-to-40Gb/s quarter-rate NRZ/PAM4 dual-mode transmitter in 14nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 58, Issue , 2015, Pages 60-61

  Kim, Jihwan ^a   Balankutty, Ajay ^a   Elshazly, Amr ^a   Huang, Yan Yu ^a   Song, Hang ^a   Yu, Kai ^a   O'Mahony, Frank ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL STORAGE; ERROR CORRECTION; FIR FILTERS; MODULATION; PULSE AMPLITUDE MODULATION; TRANSMITTERS;

CMOS PROCESS TECHNOLOGY; NETWORKING APPLICATIONS; PHASE ERROR DETECTION; QUADRATURE ERROR CORRECTION; SIGNAL INTEGRITY; TRANSMITTERS (TX); WIDE FREQUENCY RANGE; WIRE-LINE COMMUNICATIONS;

CMOS INTEGRATED CIRCUITS;

EID: 84938594374     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2015.7062925     Document Type: Conference Paper

References (7)

1. Optical Interconnect Forum (OIF) [Online]. Available: http://www.oiforum.com/public/currentprojects.html
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3. A. A. Hafez, et al., "A 32-to-48Gb/s Serializing Transmitter Using Multiphase Sampling in 65nm CMOS," ISSCC Dig. Tech. Papers, pp. 38-39, Feb. 2013.
4. C. Menolfi, et al., "A 28Gb/s Source-Series Terminated TX in 32nm CMOS SOI," ISSCC Dig. Tech. Papers, pp. 334-335, Feb. 2012.
5. A. Elshazly, et al., "A 2GHz-to-7.5GHz Quadrature Clock-Generator Using Digital Delay Locked Loops for Multi-Standard I/Os in 14nm CMOS," IEEE Symp. VLSI Circuits, pp. 52-53, June 2014.
6. T.-C. Hsueh, et al., "A 25.6Gb/s Differential and DDR4/GDDR5 Dual-Mode Transmitter with Digital Clock Calibration in 22nm CMOS," ISSCC Dig. Tech. Papers, pp. 444-445, Feb. 2014.
7. M. Mansuri, el al., "An On-Die All-Digital Delay Measurement Circuit with 250fs Accuracy," IEEE Symp. VLSI Circuits, pp. 98-99, June 2012.