A 28Gb/s source-series terminated TX in 32nm CMOS SOI

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 334-335

  Menolfi, Christian ^a   Hertle, Juergen ^b   Toifl, Thomas ^a   Morf, Thomas ^a   Gardellini, Daniele ^b   Braendli, Matthias ^a   Buchmann, Peter ^a   Kossel, Marcel ^a  

^a IBM   (Switzerland)

^b Miromico   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

ATTRACTIVE SOLUTIONS; COMPLEMENTARY OUTPUT; DATA RATES; DELAY MISMATCH; HALF-RATE; LOW-POWER CONSUMPTION; SINGLE-ENDED; TRANSMITTER CIRCUITS;

DATA COMMUNICATION SYSTEMS;

TOPOLOGY;

EID: 84860689554     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6177035     Document Type: Conference Paper

References (5)

1. G. Ono et al., "10:4 MUX and 4:10 DEMUX gearbox LSI for 100-Gigabit Ethernet link", ISSCC Dig. Tech. Papers, pp. 148-149, Feb. 2011.
2. N. Nedovic et al., "A 2x22.3Gb/s SerDes in 65nm CMOS technology", IEEE Symp. VLSI Circuits, pp. 10-11, Jun. 2009.
3. A. Amirkhany et al., "A 24Gb/s software programmable multi-channel transmitter", IEEE Symp. VLSI Circuits, pp. 38-39, Jun., 2007.
4. C. Menolfi et al., "A 16Gb/s source-series terminated transmitter in 65nm CMOS SOI", ISSCC Dig. Tech. Papers, pp. 446-447, Feb. 2007.
5. M. Kossel et al., "A T-coil-enhanced 8.5 Gb/s high-swing SST transmitter in 65 nm bulk CMOS with <-16 dB return loss over 10 GHz bandwidth", J. Solid-State Circuits, vol. 43, Dec 2008, pp. 2905-2920.