A 32-to-48Gb/s serializing transmitter using multiphase sampling in 65nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 56, Issue , 2013, Pages 38-39

  Hafez, Amr Amin ^a   Chen, Ming Shuan ^a   Yang, Chih Kong Ken ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA RATES; HOLD TIME; LAST STAGE; MULTI-PHASE SAMPLING; OPERATING RANGES; POWER PENALTY; SERIALIZERS; TIMING CONSTRAINTS;

OPTICAL TRANSCEIVERS; TRANSMITTERS;

TIMING CIRCUITS;

EID: 84876564225     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2013.6487627     Document Type: Conference Paper

References (5)

1. Kouichi Kanda et al., "A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3580-3587, Dec. 2009.
2. Shunichi Kaeriyama et al., "A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems," IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3568-3579, Dec. 2009.
3. Amr A. Hafez, Ming-Shuan Chen, C.-K. Ken Yang, "A Multi-Phase Multi-frequency Clock Generator Using Superharmonic Injection Locked Multipath Ring Oscillators as Frequency Dividers," IEEE Asian Solid State Circuits Conference (ASSCC), pp. 289-292, Nov. 2012.
4. Amr A. Hafez and C.-K. Ken Yang, "Design and Optimization of Multipath Ring Oscillators," IEEE Trans. Circuits and Systems-I: Regular Papers, vol. 58, no. 10, pp. 2332-2345, Oct. 2011.
5. Jeong-Kyoum Kim, Jaeha Kim, Gyudong Kim, and Deog-Kyoon Jeong, "A Fully Integrated 0.13-μm CMOS 40-Gb/s Serial Link Transceiver," IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1510-1521, May 2009.