Cause of erase speed degradation during two-bit per cell operation of a trapping nitride storage flash memory cell

IEEE International Reliability Physics Symposium Proceedings

Volumn 2004-January, Issue January, 2004, Pages 522-526

  Tsai, W J ^b   Zous, N K ^a,b   Chou, M H ^a,b   Huang, Smile ^a,b   Chen, H Y ^a,b   Yeh, Y H ^a,b   Liu, M Y ^a,b   Yeh, C C ^b   Wang, T ^b   Ku, Joseph ^a,b   Lu, Chih Yuan ^a,b  

^a MACRONIX INTERNATIONAL CO LTD   (Taiwan)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Endurance; Erase speed degradation; Flash memory; MXVAND; NROM; ONO; Over erasure; PHINES; Program erasecycling; SONOS; Trapping nitride storage; Two bit per cell

Indexed keywords

CELLS; CYTOLOGY; DURABILITY; MEMORY ARCHITECTURE; MONOLITHIC MICROWAVE INTEGRATED CIRCUITS; NITRIDES; SEMICONDUCTOR STORAGE;

MXVAND; NITRIDE STORAGE; NROM; ONO; OVER-ERASURE; PHINES; PROGRAM/ERASECYCLING; SONOS;

FLASH MEMORY;

EID: 84932116134     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2004.1315383     Document Type: Conference Paper

References (13)

1. B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, "Can NROM, a 2 Bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells, " in Exten. Abst. 1999 Conf. Solid State Devices and Materials, 1999, pp. 522-524.
2. W.J. Tsai, N.K. Zous, C.J. Liu, C.C. Liu, C.H. Chen, Tahui Wang, Sam Pan, and Chih-Yuan Lu, "Data Retention Behavior of a SONOS Type Two-Bit Storage Flash Memory Cell, " in IEDM Tech. Digest, 2001, pp. 719-722.
3. C.C. Yeh, W.J. Tsai, M.I. Liu, T.C. Lu, S.K. Cho, C.J. Lin, Tahui Wang, Sam Pan, and Chih-Yuan Lu, "PHINES: A Novel Low Power Program/Erase, Small Pitch, 2-Bit per Cell Flash Memory, " in IEDM Tech. Digest, 2002, pp. 931-934.
4. M.H. White, D. Adams, and J. Bu, "On the Go With SONOS, " in IEEE Circuits and Devices Magazine, Vol.16, 2000, pp. 22-31.
5. M.K. Cho and D.M. Kim, "High Performance SONOS Memory Cells Free of Drain Tum-on and Over-Erase: Compatibility Issue with Current Flash Technology, " in IEEE Elec. Dev. Lett., Vol.21, 2000, pp. 399-401.
6. W.J. Tsai, S.H. Gu, N.K. Zous, C.C. Yeh, C.C. Liu, C.H. Chen, Tahui Wang, Sam Pan, and Chih-Yuan Lu, "Cause of Data Retention Loss in a Nitride-Based Localized Trapping Storage Flash Memory Cell, " in Proc. Int. Reliability Phys. Symp., 2002, pp. 34-38.
7. Meir Jannai, "Data Retention, Endurance and Acceleration Factors of NROM Devices", in Proc. Int. Reliability Phys. Symp., 2003, pp. 502-505.
8. W.J. Tsai, C.C. Yeh, N.K. Zou, C.C. Liu, S.K. Cho, C.H. Chen, Tahui Wang, Sam Pan, and Chih-Yuan Lu, "Hot Carrier Enhanced Read Disturb and Scaling Effects in a Localized Trapping Storage SONOS Type Flash Memory Cell", in Exten. Abst. 2002 Conf. Solid State Devices and Materials, 2002, pp. 164-165.
9. E. Aloni, M. Gutman, Y. Roizin, D. Finzi, and Choi II Hyun, "Endurance Enhancement in microFlash Memory Device, " in Exten. Abst. 2000 Conf. Solid State Devices and Materials, 2000, pp. 298-299.
10. T. Wang, L.P. Chiang, N.K. Zous, T.E. Chang, and C. Huang, "Characterization of Various Stress-Induced Oxide Traps in MOSFET's by Using a Novel Transient Current Technique, " in IEDM Tech. Digest, 1997, pp. 89-92.
11. T. Wang, T.E. Chang, L.P. Chiang, C.H. Wang, N.K. Zous, and C. Huang, "Investigation of Oxide Charge Trapping and Detrapping in a MOSFET by Using a GIDL Current Technique, " in IEEE Trans. Elec. Dev., 1998, pp. 1511-1517.
12. Synopsis, "MEDICI Device Simulator, " 2003.
13. J. Chen, J. Hsu, S. Luan, Y. Tang, D. Liu, S. Haddad, C. Chang, S. Longcor, and J. Lien, "Short Channel Enhanced Degradation During Discharge of Flash EEPROM Memory Cell, " in IEDM Tech. Digest, 1995, pp. 331-334.