Seesaw: An area-optimized FPGA viterbi decoder for PUFs

Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014

Volumn , Issue , 2014, Pages 387-393

  Hiller, Matthias ^a   Lima, Leandro Rodrigues ^a   Sigl, Georg ^a  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

Author keywords

Convolutional Code; Error Correction; FPGA; Physical Unclonable Functions (PUFs); Viterbi Algorithm; VLSI

Indexed keywords

CONVOLUTION; CONVOLUTIONAL CODES; CRYPTOGRAPHY; DECODING; ERROR CORRECTION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE SECURITY; MEMORY ARCHITECTURE;

CRYPTOGRAPHIC KEY; DATA ACCESS PATTERNS; INTERMEDIATE RESULTS; SECURITY PRIMITIVES; STATE OF THE ART; VITERBI DECODER; VITERBI DECODING; VLSI;

VITERBI ALGORITHM;

EID: 84928796196     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2014.33     Document Type: Conference Paper

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