A reconfigurable, power-efficient adaptive Viterbi decoder

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 4, 2005, Pages 484-488

  Tessier, Russell ^a   Swaminathan, Sriram ^a   Ramaswamy, Ramaswamy ^a   Goeckel, Dennis ^a   Burleson, Wayne ^a  

^a University of Massachusetts Amherst   (United States)

Author keywords

Dynamic reconfiguration; Field programmable gate array (FPGA); Viterbi algorithm (VA)

Indexed keywords

ADAPTIVE ALGORITHMS; BIT ERROR RATE; CONVOLUTIONAL CODES; ELECTRIC POWER UTILIZATION; ERROR ANALYSIS; ERROR CORRECTION; FIELD PROGRAMMABLE GATE ARRAYS; SPURIOUS SIGNAL NOISE;

DECODING ALGORITHMS; DYNAMIC RECONFIGURATION; POWER-SENSITIVE SYSTEMS; VITERBI ALGORITHM (VA);

DATA TRANSFER;

EID: 16444378607     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.842930     Document Type: Article

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