Performance and security evaluation of AES S-box-based glitch PUFs on FPGAs

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 7644 LNCS, Issue , 2012, Pages 45-62

  Yamamoto, Dai ^a,b   Hospodar, Gabriel ^a   Maes, Roel ^a   Verbauwhede, Ingrid ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

^b FUJITSU LABORATORIES LTD   (Japan)

Author keywords

Authentication; FPGA; Glitch PUF; Key Generation; Performance; Security

Indexed keywords

CHALLENGE-RESPONSE PAIR; GLITCH GENERATOR; GLITCH PUF; KEY GENERATION; PERFORMANCE; SECURITY; SECURITY APPLICATION; SECURITY EVALUATION; VOLTAGE VARIATION;

AUTHENTICATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); RESEARCH;

CRYPTOGRAPHY;

EID: 84868338014     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-34416-9_4     Document Type: Conference Paper

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