Trace-driven simulation of multithreaded applications

ISPASS 2011 - IEEE International Symposium on Performance Analysis of Systems and Software

Volumn , Issue , 2011, Pages 87-96

  Rico, Alejandro ^a   Duran, Alejandro ^a   Cabarcas, Felipe ^a,c   Etsion, Yoav ^a   Ramirez, Alex ^a,b   Valero, Mateo ^a,b  

^a BARCELONA SUPERCOMPUTING CENTER   (Spain)

^b UNIVERSITAT POLITÈCNICA DE CATALUNYA   (Spain)

^c UNIVERSIDAD DE ANTIOQUIA   (Colombia)

Author keywords

[No Author keywords available]

Indexed keywords

EXECUTION-DRIVEN SIMULATION; HARDWARE SUPPORTS; INTRINSIC BEHAVIOR; MULTI-THREADED APPLICATION; MULTITHREADED; PROGRAMMING MODELS; RESEARCH OPPORTUNITIES; SIMULATION FRAMEWORK; SIMULATION METHODOLOGY; SIMULATION TIME; TRACE DRIVEN SIMULATION;

COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING; COMPUTER SOFTWARE; RESEARCH; SCHEDULING; TRACE ANALYSIS;

COMPUTER SIMULATION;

EID: 79957528059     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2011.5762718     Document Type: Conference Paper

References (21)

1. M. Pavlovic, Y. Etsion, and A. Ramirez, "Can Manycores Support the Memory Requirements of Scientific Applications?" in A4MMC'10: 1st Workshop on Applications for Multi and Many Core Processors, 2010.
2. R. M. Fujimoto, "Parallel discrete event simulation," in WSC '89: Proceedings of the 21st conference on Winter simulation, 1989, pp. 19-28.
3. R. D. Blumofe, C. F. Joerg, B. C. Kuszmaul, C. E. Leiserson, K. H. Randall, and Y. Zhou, "Cilk: an efficient multithreaded runtime system," SIGPLAN Not., vol. 30, no. 8, pp. 207-216, 1995.
4. A. Rico, F. Cabarcas, A. Quesada, M. Pavlovic, A. J. Vega, Y. Etsion, and A. Ramirez, "Scalable simulation of decoupled accelerator architectures," Universitat Politècnica de Catalunya, Tech. Rep. UPC-DACRR-2010-14, 2010.
5. "Nanos++ project website," http://nanos.ac.upc.edu/projects/ nanox.
6. P. Bellens, J. M. Perez, R. M. Badia, and J. Labarta, "CellSs: a Programming Model for the Cell BE Architecture," in SC '06: Proceedings of the 2006 ACM/IEEE Conference on Supercomputing, 2006, p. 86.
7. J. M. Perez, R. M. Badia, and J. Labarta, "A Dependency-Aware Task-Based Programming Environment for Multi-Core Architectures," in Proceedings of the 2008 IEEE International Conference on Cluster Computing, 2008, pp. 142-151.
8. "Mercurium project website," http://nanos.ac.upc.edu/content/ mercurium-compiler.
9. C. keung Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. Janapa, and R. K. Hazelwood, "Pin: Building customized program analysis tools with dynamic instrumentation," in Programming Language Design and Implementation, 2005, pp. 190-200.
10. L. Blackford, J. Demmel, J. Dongarra, I. Duff, S. Hammarling, G. Henry, M. Heroux, L. Kaufman, A. Lumsdaine, A. Petitet et al., "An updated set of basic linear algebra subprograms (BLAS)," ACM Transactions on Mathematical Software (TOMS), vol. 28, no. 2, pp. 135-151, 2002.
11. A. Rico, A. Ramirez, and M. Valero, "Available Task-level Parallelism on the Cell BE," Scientific Programming, vol. 17, no. 1-2, pp. 59-76, 2009.
12. S. Borkar, "Thousand core chips: a technology perspective," in DAC '07: Proceedings of the 44th annual Design Automation Conference, 2007, pp. 746-749.
13. K. Fatahalian, D. R. Horn, T. J. Knight, L. Leem, M. Houston, J. Y. Park, M. Erez, M. Ren, A. Aiken, W. J. Dally, and P. Hanrahan, "Sequoia: programming the memory hierarchy," in SC '06: Proceedings of the 2006 ACM/IEEE conference on Supercomputing, 2006, p. 83.
14. J. Reinders, Intel threading building blocks. O'Reilly, 2007.
15. P. Charles, C. Grothoff, V. Saraswat, C. Donawa, A. Kielstra, K. Ebcioglu, C. von Praun, and V. Sarkar, "X10: an object-oriented approach to non-uniform cluster computing," in OOPSLA '05: Proceedings of the 20th annual ACM SIGPLAN conference on Object-oriented programming, systems, languages, and applications, 2005, pp. 519-538.
16. S. Kumar, C. J. Hughes, and A. Nguyen, "Carbon: architectural support for fine-grained parallelism on chip multiprocessors," in ISCA '07: Proceedings of the 34th annual international symposium on Computer architecture, 2007, pp. 162-173.
17. P. S. Magnusson, M. Christensson, J. Eskilson, D. Forsgren, G. Hållberg, J. Högberg, F. Larsson, A. Moestedt, and B. Werner, "Simics: A Full System Simulation Platform," IEEE Computer, vol. 35, no. 2, pp. 50-58, 2002.
18. J. Renau, B. Fraguela, J. Tuck, W. Liu, M. Prvulovic, L. Ceze, S. Sarangi, P. Sack, K. Strauss, and P. Montesinos, "SESC simulator," http://sesc.sourceforge.net, 2005.
19. T. Austin, E. Larson, and D. Ernst, "SimpleScalar: An Infrastructure for Computer System Modeling," IEEE Computer, vol. 35, no. 2, pp. 59-67, 2002.
20. N. L. Binkert, R. G. Dreslinski, L. R. Hsu, K. T. Lim, A. G. Saidi, and S. K. Reinhardt, "The M5 Simulator: Modeling Networked Systems," IEEE Micro, vol. 26, no. 4, pp. 52-60, 2006.
21. E. Argollo, A. Falcón, P. Faraboschi, M. Monchiero, and D. Ortega, "COTSon: infrastructure for full system simulation," SIGOPS Oper. Syst. Rev., vol. 43, no. 1, pp. 52-61, 2009.