Automatic TLM generation for early validation of multicore sSystems

IEEE Design and Test of Computers

Volumn 28, Issue 3, 2011, Pages 10-19

  Abdi, Samar ^a   Schirner, Gunar ^b   Hwang, Yonghyun ^c   Gajski, Daniel D ^d   Yu, Lochi ^e  

^a Civil and Environmental Engineering   (Canada)

^b Qualcomm ^*  (United States)

^c UNIVERSIDAD DE COSTA RICA   (Costa Rica)

^d NORTHEASTERN UNIVERSITY   (United States)

^e UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

design and test; embedded systems; multicore design; TLM; transaction level modeling

Indexed keywords

DESIGN AND TESTS; MULTI CORE; MULTI-CORE PLATFORMS; MULTICORE DESIGN; S-SYSTEMS; SOFTWARE APPLICATIONS; SOFTWARE VENDORS; TLM; TRANSACTION LEVEL MODELING; TRANSACTION-LEVEL MODEL; VIRGINIA TECH.;

AUTOMATIC TEST PATTERN GENERATION; DISPENSERS; EMBEDDED SOFTWARE; SOFTWARE TESTING;

EMBEDDED SYSTEMS;

EID: 79956279112     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2010.117     Document Type: Article

References (11)

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