Ultra-low voltage datapath blocks in 28nm UTBB FD-SOI

2014 IEEE Asian Solid-State Circuits Conference, A-SSCC - Proceedings of Technical Papers

Volumn , Issue , 2015, Pages 49-52

  Reyserhove, Hans ^a   Reynders, Nele ^a   Dehaene, Wim ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

ECONOMIC AND SOCIAL EFFECTS; ENERGY UTILIZATION;

BACK-GATE BIASING; ENERGY PERFORMANCE; LEAKAGE REDUCTION; MINIMUM ENERGY POINT; MULTIPLY ACCUMULATE; REDUCE ENERGY CONSUMPTION; STATE OF THE ART; ULTRA-LOW-VOLTAGE;

FINITE DIFFERENCE METHOD;

EID: 84922511566     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2014.7008857     Document Type: Conference Paper

References (5)

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2. N. Reynders and W. Dehaene, "Variation-Resilient Building Blocks for Ultra-Low-Energy Sub-Threshold Design," Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 59, no. 12, pp. 898-902, Dec 2012.
3. D. Jacquet, et al., "A 3 GHz Dual Core Processor ARM Cortex TM-A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization," Solid-State Circuits, IEEE Journal of, vol. 49, no. 4, pp. 812-826, April 2014.
4. N. Reynders and W. Dehaene, "Variation-resilient sub-threshold circuit solutions for ultra-low-power Digital Signal Processors with 10MHz clock frequency," in ESSCIRC, Proceedings of the, Sept 2012, pp. 474-477.
5. G. de Streel and D. Bol, "Impact of back gate biasing schemes on energy and robustness of ULV logic in 28nm UTBB FDSOI technology," in ISLPED, IEEE International Symposium on, Sept 2013, pp. 255-260.