Variation-resilient sub-threshold circuit solutions for ultra-low-power Digital Signal Processors with 10MHz clock frequency

European Solid-State Circuits Conference

Volumn , Issue , 2012, Pages 474-477

  Reynders, Nele ^a   Dehaene, Wim ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; CIRCUIT SOLUTION; CLOCK FREQUENCY; DESIGN STRATEGIES; DIFFERENTIAL TRANSMISSION; MINIMUM ENERGY; SUBTHRESHOLD; ULTRA-LOW POWER;

CLOCKS; ENERGY UTILIZATION; SIGNAL PROCESSING;

LOW POWER ELECTRONICS;

EID: 84870773704     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2012.6341358     Document Type: Conference Paper

References (5)

1. M. Ashouei et al., "A voltage-scalable biomedical signal processor running ECG using 13pJ/cycle at 1MHz and 0.4V," in ISSCC, Feb. 2011, pp. 332-334.
2. N. Reynders and W. Dehaene, "A 190mV supply, 10MHz, 90nm CMOS, pipelined sub-threshold adder using variation-resilient circuit techniques," in A-SSCC, Nov. 2011, pp. 113-116.
3. O. Weiss, M. Gansen, and T. Noll, "A flexible datapath generator for physical oriented design," in ESSCIRC, Sept. 2001, pp. 393-396.
4. M. Hatamian and G. Cash, "A 70-MHz 8-bitx8-bit parallel pipelined multiplier in 2.5-μm CMOS," JSSC, vol. 21, no. 4, pp. 505-513, 1986.
5. J. Kao, M. Miyazaki, and A. Chandrakasan, "A 175-mV multiplyaccumulate unit using an adaptive supply voltage and body bias architecture," JSSC, vol. 37, no. 11, pp. 1545-1554, Nov. 2002.