Precise shared cache analysis using optimal interference placement

Real-Time Technology and Applications - Proceedings

Volumn 2014-October, Issue October, 2014, Pages 125-134

  Nagar, Kartik ^a   Srikant, Y N ^a  

^a INDIAN INSTITUTE OF SCIENCE   (India)

Author keywords

[No Author keywords available]

Indexed keywords

INTERACTIVE COMPUTER SYSTEMS; MULTICORE PROGRAMMING; REAL TIME SYSTEMS;

MICRO-ARCHITECTURAL ANALYSIS; MULTICORE ARCHITECTURES; PRECISION IMPROVEMENT; PROGRAM POINTS; SHARED RESOURCES; STATE OF THE ART; WORST CASE INTERFERENCE POINTS; WORST-CASE EXECUTION TIME;

COMPUTER ARCHITECTURE;

EID: 84919794738     PISSN: 10801812     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTAS.2014.6925996     Document Type: Conference Paper

References (17)

1. Damien Hardy, Thomas Piquet, and Isabelle Puaut. Using bypass to tighten WCET estimates for multi-core processors with shared instruction caches. In RTSS, 2009.
2. Yan-Tsun Steven Lee and Sharad Malik. Performance analysis of embedded software using implicit path enumeration. In DAC, 1995.
3. Xianfeng Li, Yun Liang, Tulika Mitra, and Abhik Roychoudury. Chronos: A timing analyzer for embedded software. Science of Computer Programming, 69(1-3):56-67, 2007. http://www.comp.nus.edu.sg/~rpembed/chronos.
4. Jun Yan and Wei Zhang. WCET analysis for multi-core processors with shared 12 instruction caches. In RTAS, 2008.
5. Jun Yan and Wei Zhang. Accurately estimating worst-case execution time for multi-core processors with shared direct-mapped instruction caches. In RTCSA, 2009.
6. Yan Li, Vivy Suhendra, Yun Liang, Tulika Mitra, and Abhik Roychoudhury. Timing analysis of concurrent programs running on shared cache multi-cores. In RTSS, 2009.
7. Sudipta Chattopadhyay, Chong Lee Kee, Abhik Roychoudhury, Timon Kelter, Marwedel Peter, and Falk Heiko. A unified WCET analysis framework for multi-core platforms. In RTAS, 2012.
8. Sudipta Chattopadhyay and Abhik Roychoudhury. Scalable and precise refinement of cache timing analysis via model checking. In RTSS, 2011.
9. Vivy Suhendra and Tulika Mitra. Exploring locking and partitioning for predictable shared caches on multi-cores. In DAC, 2008.
10. Marco Paolieri, Eduardo Quinones, Franciso J. Cazorla, Guillem Bernat, and Mateo Valero. Hardware support for WCET analysis of hard real-time multicore systems. In ISCA, 2009.
11. Man-ki Yoon, Jung-Eun Kim, and Sha Lui. Optimizing tunable WCET with shared resource allocation and arbitration in hard real-time multicore systems. In RTSS, 2011.
12. Bryan C. Ward, Jonathan L. Herman, Christopher J. Kenna, and James H. Anderson. Making shared caches more predictable on multicore platforms. In ECRTS, 2013.
13. Nan Guan, Martin Stigge, Wang Yi, and Ge Yu. Cache-aware scheduling and analysis for multicores. In EMSOFT, 2012.
14. Damien Hardy and Isabelle Puaut. WCET analysis of multi-level non-inclusive set-associative instruction caches. In RTSS, 2008.
15. Yan-Tsun Steven Lee, Sharad Malik, and Andrew Wolfe. Efficient microarchitecture modeling and path analysis for real-time software. In RTSS, 1995.
16. Yan-Tsun Steven Lee, Sharad Malik, and Andrew Wolfe. Cache modeling for real-time software: Beyond direct mapped instruction caches. In RTSS, 1996.
17. WCET projects / benchmarks. http://www.mrtc.mdh.se/projects/wcet/benchmarks.html.