A 14 bit 1 GS/s RF sampling pipelined ADC with background calibration

IEEE Journal of Solid-State Circuits

Volumn 49, Issue 12, 2014, Pages 2857-2867

  Ali, Ahmed M A ^a   Dinc, Huseyin ^a   Bhoraskar, Paritosh ^a   Dillon, Chris ^a   Puckett, Scott ^a   Gray, Bryce ^a   Speir, Carroll ^a   Lanford, Jonathan ^a   Brunsilius, Janet ^a   Derounian, Peter R ^a   Jeffries, Brad ^a   Mehta, Ushma ^a   McShea, Matthew ^a   Stop, Russell ^a  

^a ANALOG DEVICES INC   (United States)

Author keywords

A D converter; ADC; background calibration; distortion cancellation; kick back; pipeline; RF sampling; SHA less

Indexed keywords

CALIBRATION; CMOS INTEGRATED CIRCUITS; PIPELINES;

A/D CONVERTER; ADC; BACKGROUND CALIBRATIONS; DISTORTION CANCELLATION; KICK-BACK; RF SAMPLING; SHA-LESS;

ANALOG TO DIGITAL CONVERSION;

EID: 84913537076     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2014.2361339     Document Type: Article

References (12)

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