SPINDLE: SPINtronic deep learning engine for large-scale neuromorphic computing

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2014, Pages 15-20

  Ramasubramanian, Shankar Ganesh ^a   Venkatesan, Rangharajan ^a   Sharad, Mrigank ^a   Roy, Kaushik ^a   Raghunathan, Anand ^a  

^a Purdue University   (United States)

Author keywords

Emerging devices; Nanoelectronics; Neural networks; Neuromorphic computing; Post CMOS; Spintronics

Indexed keywords

CMOS INTEGRATED CIRCUITS; LEARNING SYSTEMS; LOW POWER ELECTRONICS; NANOELECTRONICS; NEURAL NETWORKS; NEURONS; OBJECT RECOGNITION;

EMERGING DEVICES; FUNDAMENTAL BUILDING BLOCKS; HANDWRITING RECOGNITION; NEUROMORPHIC COMPUTING; POST-CMOS; PROGRAMMABLE PROCESSORS; REDUCTION IN ENERGY CONSUMPTION; STORAGE REQUIREMENTS;

MAGNETOELECTRONICS;

EID: 84906812702     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2627369.2627625     Document Type: Conference Paper

References (24)

1. Y. LeCun et al. Gradient-based learning applied to document recognition. In Proc. IEEE, 1998.
2. G. Hinton et al. A fast learning algorithm for deep belief nets. Trans. Neural Computation, 2006.
3. Y. Bengio. Learning deep architectures for AI. Foundations and Trends in Machine Learning, 2009.
4. George Rosenberg. Improving photo search: A step across the semantic gap http://googleresearch.blogspot.com/2013/06/ improving-photo-search-step-across. html. June 2009.
5. Y. Netzer et al. Reading digits in natural images with unsupervised feature learning. In NIPS Workshop on Deep Learning and Unsupervised Feature Learning, 2011.
6. J. Bergstra. Theano: Deep learning on GPUs with Python. In Big Learn workshop NIPS, 2011.
7. M. Sankaradas et al. A massively parallel coprocessor for convolutional neural networks. In Proc. ASAP, 2009.
8. C. Farabet et al. Hardware accelerated convolutional neural networks for synthetic vision systems. In Proc. ISCAS, 2010.
9. E. Chen et al. Advances and future prospects of spin-transfer torque random access memory. IEEE Trans. Magnetics, (6): 1873-1878, June 2010.
10. M. Sharad et al. Boolean and non-boolean computation with spin devices. In Proc. IEDM, 2012.
11. M. Sharad et al. Spin neuron for ultra low power computational hardware. In Proc. DRC, 2012.
12. T. Kimura et al. Switching magnetization of a nanoscale ferromagnetic particle using nonlocal spin injection. Phys. Rev. Lett., 2006.
13. R. Venkatesan et al. DWM-TAPESTRI - An energy efficient all-spin cache using domain wall shift based writes. In Proc. DATE, 2013.
14. G.D. Panagopoulos et al. Physics-Based SPICE-Compatible Compact Model for Simulating Hybrid MTJ/CMOS Circuits. Trans. TED, 2013.
15. L Gao et al. Analog-input analog-weight dot-product operation with Ag/a-Si/Pt memristive devices. In Proc. VLSI-SoC, 2012.
16. CACTI, http://www.hpl.hp.com/research/cacti/.
17. R. Venkatesan et al. TapeCache: A High Density, Energy Efficient Cache Based on Domain Wall Memory. In Proc. ISLPED, 2012.
18. R. Collobert et al. Torch7: A Matlab-like environment for machine learning. In BigLearn, NIPS Workshop, 2011.
19. Alex Krizhevsky. Learning multiple layers of features from tiny images. Technical report, 2009.
20. E. Painkras et al. Spinnaker: A multi-core system-on-chip for massively-parallel neural net simulation. In Proc. CICC, 2012.
21. J. Seo et al. A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. In Proc. CICC, 2011.
22. B. Rajendran et al. Specifications of nanoscale devices and circuits for neuromorphic computational systems. Trans. TED, 2013.
23. D. Kuzum et al. Nanoelectronic programmable synapses based on phase change materials for brain-inspired computing. Nano Letters, 2012.
24. S. H. Jo et al. Nanoscale memristor device as synapse in neuromorphic systems. Nano Letters, 2010.