20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 57, Issue , 2014, Pages 234-235

  Yabuuchi, Makoto ^a   Tsukamoto, Yasumasa ^a   Morimoto, Masao ^a   Tanaka, Miki ^a   Nii, Koji ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADVANCED TECHNOLOGY; NEGATIVE BIT LINE; OPERATING MARGINS; OPERATIONAL WINDOWS; PROCESS TECHNOLOGIES; SRAM CELL TRANSISTORS; STATIC NOISE MARGIN; TRANSISTOR CHARACTERISTICS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84898073553     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2014.6757414     Document Type: Conference Paper

References (5)

1. E. Karl, et al., "A 4.6GHz 162Mb SRAM Design in 22nm Tri-Gate CMOS Technology with Integrated Active VMIN-Enhancing Assist Circuitry, " in ISSCC Dig., pp. 230-231, Feb. 2012.
2. J. Chang, et al., "A 20nm 112Mb SRAM in High-k Metal-Gate with Assist Circuitry for Low-Leakage and Low-VMIN Applications, " in ISSCC Dig., pp. 316-317, Feb. 2013.
3. H. Pilo, et al., "A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements," in ISSCC Dig., pp. 254-256, Feb. 2011.
4. H. Fujiwara, et al., "A 20nm 0.6V 2.1μW/MHz 128kb SRAM with no half select issue by interleave wordline and hierarchical bitline scheme," in Symp. VLSI Circuits, pp. 118-119, June 2013.
5. Y. Ishii, et al., "A 28nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues," JSSC, pp. 2535-2544, Nov. 2011.