A 20nm 0.6V 2.1μW/MHz 128kb SRAM with no half select issue by interleave wordline and hierarchical bitline scheme

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2013, Pages

  Fujiwara, H ^a   Yabuuchi, M ^a   Morimoto, M ^a   Tanaka, K ^a   Tanaka, M ^a   Maeda, N ^a   Tsukamoto, Y ^a   Nii, K ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE POWER; BIT LINES; LEAKAGE POWER; LEAKAGE POWER REDUCTION; SRAM MACRO; WORDLINES;

EID: 84883368407     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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5. M. Yamaoka, et al., ESSCIRC, pp. 286-289, 2008.
6. M. E. Sinangil, et al., ISSCC, pp. 260-262, 2011.