A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 57, Issue , 2014, Pages 196-197

  Tai, Hung Yen ^a   Hu, Yao Sheng ^a   Chen, Hung Wei ^a   Chen, Hsin Shu ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; COMPARATORS (OPTICAL); DIGITAL INTEGRATED CIRCUITS; ENERGY EFFICIENCY; WIRELESS SENSOR NETWORKS;

ANALOG TO DIGITAL CONVERTERS; ELECTRONIC DEVICE; LOW SUPPLY VOLTAGES; SIGNAL CONDITION; SUCCESSIVE APPROXIMATION REGISTER; SWITCHING METHODS; SWITCHING TECHNIQUES; VOTING TECHNIQUES;

LOW POWER ELECTRONICS;

EID: 84898073172     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2014.6757397     Document Type: Conference Paper

References (6)

1. C.-Y. Liou and C.-C. Hsieh, "A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with Charge-Average Switching DAC in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 280-281, Feb. 2013.
2. P. Harpe, et al., "A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven Noise Reduction," ISSCC Dig. Tech. Papers, pp. 270-271, Feb. 2013.
3. C.-C. Liu, et al., "A 10b 100MS/s 1.13mW SAR ADC with Binary-Scaled Error Compensation," ISSCC Dig. Tech. Papers, pp. 386-387, Feb. 2010.
4. M. Yip and A. P. Chandrakasan, "A Resolution-Reconfigurable 5-to-10b 0.4-to-1V Power Scalable SAR ADC," ISSCC Dig. Tech. Papers, pp. 190-191, Feb. 2011.
5. V. Hariprasath, et al., "Merged Capacitor Switching Based SAR ADC with Highest Switching Energy-Efficiency," IET Electronics Letters, Apr. 2010.
6. M. van Elzakker, et al., "A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC," ISSCC Dig. Tech. Papers, pp. 244-245, Feb. 2008.