An 860µW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 57, Issue , 2014, Pages 172-173

  Chillara, Vamshi Krishna ^a,b,c   Liu, Yao Hong ^a   Wang, Bindi ^a,b   Ba, Ao ^a   Vidojkovic, Maja ^a   Philips, Kathleen ^a   De Groot, Harmke ^a   Staszewski, Robert Bogdan ^b  

^a HOLST CENTRE   (Netherlands)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^c ANALOG DEVICES   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

SENSOR NODES; TRANSCEIVERS;

AUTONOMOUS SENSORS; FREQUENCY MODULATORS; FREQUENCY SYNTHESIS; NANO-SCALE CMOS; SHORT-RANGE NETWORKS; TIME TO DIGITAL CONVERTERS; ULTRA-LOW POWER; WIRELESS PERSONAL AREA NETWORKS;

LOW POWER ELECTRONICS;

EID: 84898064885     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2014.6757387     Document Type: Conference Paper

References (7)

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3. N. Pavlovic, et al., "A 5.3GHz Digital-to-Time-Converter-Based Fractional-N All-Digital PLL," ISSCC Dig. Tech. Papers, pp. 54-56, Feb. 2011.
4. D. Tasca, et al., "A 2.9-to-4.0GHz Fractional-N Digital PLL with Bang-Bang Phase Detector and 560fs rms Integrated Jitter at 4.5mW Power," ISSCC Dig. Tech. Papers, pp. 88-90, Feb. 2011.
5. M. Park, et al., "An Amplitude Resolution Improvement of an RF-DAC Employing Pulse-Width Modulation," IEEE Trans. Circuits and Systems-I, pp. 2590-2603, Nov. 2011.
6. J. Zhuang, et al., "A Low-Power All-Digital PLL Architecture Based on Phase Prediction," ICECS'12, pp. 797-800, Seville, Spain, Dec. 2012.
7. T. Tokairin, et al., "A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer with a Time-Windowed Time-to-Digital Converter," IEEE J. Solid-State Circuits, pp. 2582-2590, Dec. 2010.