A low-power all-digital PLL architecture based on phase prediction

2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012

Volumn , Issue , 2012, Pages 797-800

  Zhuang, Jingcheng ^a   Staszewski, Robert Bogdan ^b  

^a QUALCOMM INC   (United States)

^b DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ALL DIGITAL PHASE LOCKED LOOP; ALL-DIGITAL PLL; ARCHITECTURE-BASED; BEHAVIORAL SIMULATION; COMPLEXITY REDUCTION; DETECTION MECHANISM; FRACTIONAL PARTS; FRACTIONAL-N; FREQUENCY MULTIPLICATION; IN-FIELD; LOW POWER; PHASE DETECTION; PHASE PREDICTION; PHASE-LOCKING; PROPOSED ARCHITECTURES; REFERENCE CLOCK; TIME TO DIGITAL CONVERTERS;

FREQUENCY CONVERTERS;

CLOCKS;

EID: 84874633283     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2012.6463539     Document Type: Conference Paper

References (3)

1. R. B. Staszewski, "State-of-the-art and future directions of highperformance all-digital frequency synthesis in nanometer CMOS," IEEE Trans. on Circuits and Systems I, vol. 58, iss. 7, pp. 1497-1510, July 2011.
2. R. B. Staszewski, K. Muhammad, D. Leipold, et al., "All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS," IEEE Journal of Solid-State Circuits, vol. 39, iss. 12, pp. 2278-2291, Dec. 2004.
3. T. Tokairin, M. Okada, M. Kitsunezuka, et al., "A 2.1-to-2.8-GHz low-phase-noise all-digital frequency synthesizer with a time-windowed time-to-digital converter," IEEE Journal of Solid-State Circuits, vol. 45, no. 12, pp. 2582-2590, Dec. 2010.