A 5.3GHz digital-to-time-converter-based fractional-N all-digital PLL

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 54-55

  Pavlovic, Nenad ^a   Bergervoet, Jos ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

NETWORKS (CIRCUITS); SOLID STATE DEVICES;

ALL DIGITAL PHASE LOCKED LOOP; ALL-DIGITAL PLL; DEEP SUBMICRON CMOS; DIGITAL IMPLEMENTATION; FRACTIONAL-N; PHASE LOCKED LOOP (PLL); PHASE NOISE PERFORMANCE; TIME RESOLUTION;

PHASE LOCKED LOOPS;

EID: 79955720545     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746216     Document Type: Conference Paper

References (6)

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3. Linsay Kleeman, "The jitter model for metastability and its application to redundant synchronizers," IEEE Transaction on Computers, 39(7), pp. 930-942, July 1990.
4. R. B. Staszewski, J. L. Wallberg, S. Rezeq, et al., "All-digital PLL and transmitter for mobile phones," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2469-2480, 2005.
5. Enrico Temporiti, Colin Weltin-Wu, et al., "A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques," IEEE J. Solid-State Circuits, vol. 44, no. 3, pp.824-834, March 2009.
6. Mark A. Ferriss, Michael P. Flynn, "A 14mW Fractional-N PLL Modulator With a Digital Phase Detector and Frequency Switching Scheme," IEEE J. Solid-State Circuits, vol. 43, no. 11, pp. 2464-2471, Nov. 2008.