Retention time optimization for eDRAM in 22nm tri-gate CMOS technology

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2013, Pages

  Wang, Yih ^a   Arslan, Umut ^a   Bisnik, Nabhendra ^a   Brain, Ruth ^a   Ghosh, Swaroop ^a   Hamzaoglu, Fatih ^a   Lindert, Nick ^a   Meterelliyoz, Mesut ^a   Park, Joodong ^a   Tomishima, Shigeki ^a   Zhang, Kevin ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84894360401     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2013.6724595     Document Type: Conference Paper

References (7)

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4. Y. Aoki et al., IEDM Technical Digest, p.781-784, 2002.
5. R. Brain et al., VLSI Tech. Technical Digest, p.15, 2013.
6. C.-H. Jan et al., IEDM Technical Digest, p.44, 2012.
7. T. Sekiguchi et al., IEEE JSSC, vol. 37, p. 487, 2002.