Dynamic behavior of SRAM data retention and a novel transient voltage collapse technique for 0.6V 32nm LP SRAM

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2011, Pages

  Wang, Yih ^a   Karl, Eric ^a   Meterelliyoz, Mesut ^a   Hamzaoglu, Fatih ^a   Ng, Yong Gee ^a   Ghosh, Swaroop ^a   Wei, Liqiong ^a   Bhattacharya, Uddalak ^a   Zhang, Kevin ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DESIGNS; CO-OPTIMIZATION; DATA RETENTION; DATA RETENTION VOLTAGES; DYNAMIC BEHAVIORS; LOW POWER; LOW VOLTAGE OPERATION; OPERATING VOLTAGE; SUPPLY VOLTAGES; TRANSIENT VOLTAGE; VOLTAGE COLLAPSE; WRITE OPERATIONS;

ELECTRON DEVICES; STATIC RANDOM ACCESS STORAGE;

POWER QUALITY;

EID: 84863046376     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2011.6131655     Document Type: Conference Paper

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