A new compact analog VLSI model for Spike Timing Dependent Plasticity

IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC

Volumn , Issue , 2013, Pages 7-12

  Azghadi, Mostafa Rahimi ^a   Al Sarawi, Said ^a   Iannella, Nicolangelo ^a   Abbott, Derek ^a  

^a UNIVERSITY OF ADELAIDE   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

EXPERIMENTS; INTEGRATED CIRCUIT MANUFACTURE; PATTERN RECOGNITION;

HEBBIAN LEARNING; LEARNING MECHANISM; NEUROMORPHIC ENGINEERING; SPIKE PATTERNS; SPIKE TIMING DEPENDENT PLASTICITIES; SYMMETRIC DESIGN; SYNAPTIC PLASTICITY RULES; VERY-LARGE-SCALE INTEGRATION CIRCUITS;

VLSI CIRCUITS;

EID: 84895825360     PISSN: 23248432     EISSN: 23248440     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI-SoC.2013.6673236     Document Type: Conference Paper

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