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Proceedings -Design, Automation and Test in Europe, DATE
Volumn , Issue , 2003, Pages 30-35
Power efficiency through application-specific instruction memory transformations
Author keywords

[No Author keywords available]
Indexed keywords

EMBEDDED PROCESSORS; ENCODING TECHNIQUES; FUNCTIONAL TRANSFORMATION; INSTRUCTION MEMORY; MICROARCHITECTURAL SUPPORT; PROCESSOR PIPELINES; RE-PROGRAMMABILITY; REPROGRAMMABLE HARDWARE;
EID: 84893812369     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253583     Document Type: Conference Paper
Times cited : (1)
References (10)
  • 1
    • 0032628047 scopus 로고    scopus 로고
    • A coding framework for low-power address and data busses
    • June
    • S. Ramprasad and N. R. Shanbhag, A coding framework for low-power address and data busses, IEEE TVLSI, vol. 7, n. 2, pp. 212-221, June 1999
    • (1999) IEEE TVLSI , vol.7 , Issue.2 , pp. 212-221
    • Ramprasad, S.1    Shanbhag, N.R.2
  • 2
    • 0030644909 scopus 로고    scopus 로고
    • Asymptotic zero-Transition activity encoding for address busses in low-power microprocessor-based systems
    • March
    • L. Benini, G. De Micheli, E. Macii, D. Sciuto and C. Silvano, Asymptotic zero-Transition activity encoding for address busses in low-power microprocessor-based systems, in 7th GLS, pp. 77-82, March 1997
    • (1997) 7th GLS , pp. 77-82
    • Benini, L.1    De Micheli, G.2    Macii, E.3    Sciuto, D.4    Silvano, C.5
  • 3
    • 0034869584 scopus 로고    scopus 로고
    • Irredundant address bus encoding for low-power
    • Y. Aghaghiri, F. Fallah and M. Pedram, Irredundant address bus encoding for low-power, in ISLPED, pp. 182-187, 2001
    • (2001) ISLPED , pp. 182-187
    • Aghaghiri, Y.1    Fallah, F.2    Pedram, M.3
  • 4
    • 0034869199 scopus 로고    scopus 로고
    • Low power address encoding using self-organizing lists
    • M. Mamidipaka, D. Hirschberg and N. Dutt, Low power address encoding using self-organizing lists, in ISLPED, pp. 188-193, 2001
    • (2001) ISLPED , pp. 188-193
    • Mamidipaka, M.1    Hirschberg, D.2    Dutt, N.3
  • 5
    • 35048834531 scopus 로고
    • Bus-invert coding for low-power I/O
    • March
    • M. R. Stan andW. P. Burleson, Bus-invert coding for low-power I/O, IEEE TVLSI, vol. 3, n. 1, pp. 49-58, March 1995
    • (1995) IEEE TVLSI , vol.3 , Issue.1 , pp. 49-58
    • Stan, M.R.1    Burleson, W.P.2
  • 6
    • 0031673406 scopus 로고    scopus 로고
    • Reducing power consumption of dedicated processors through instruction set encoding
    • February
    • L. Benini, G. De Micheli, A. Macii, E. Macii and M. Poncino, Reducing power consumption of dedicated processors through instruction set encoding, in 8th GLS, pp. 8-12, February 1998
    • (1998) 8th GLS , pp. 8-12
    • Benini, L.1    De Micheli, G.2    Macii, A.3    Macii, E.4    Poncino, M.5
  • 7
    • 0033701360 scopus 로고    scopus 로고
    • Code compression for low power embedded system design
    • H. Lekatsas, J. Henkel andW.Wolf, Code compression for low power embedded system design, in DAC, pp. 294-299, 2000
    • (2000) DAC , pp. 294-299
    • Lekatsas, H.1    Henkel, J.2    Wolf, W.3
  • 8
    • 84976827033 scopus 로고
    • A data locality optimizing algorithm
    • June
    • M. E. Wolf and M. S. Lam, A Data Locality Optimizing Algorithm, in PLDI, pp. 30-44, June 1991
    • (1991) PLDI , pp. 30-44
    • Wolf, M.E.1    Lam, M.S.2
  • 10
    • 0036469652 scopus 로고    scopus 로고
    • Simplescalar: An infrastructure for computer system modeling
    • February
    • T. Austin, E. Larson and D. Ernst, SimpleScalar: An infrastructure for computer system modeling, IEEE Computer, vol. 35, n. 2, pp. 59-67, February 2002
    • (2002) IEEE Computer , vol.35 , Issue.2 , pp. 59-67
    • Austin, T.1    Larson, E.2    Ernst, D.3

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.