Design of a 3D fully-depleted SOI computational RAM

European Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 135-138

  Koob, John C ^a   Sung, Raymond J ^a   Brandon, Tyler L ^a   Elliott, Duncan G ^a   Cockburn, Bruce F ^a   McIlrath, Lisa ^b  

^a UNIVERSITY OF ALBERTA   (Canada)

^b R3Logic ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT-OPERATIONS; COMPUTATIONAL RAM; FULLY DEPLETED; FULLY DEPLETED SILICON-ON-INSULATOR; INNOVATIVE TECHNIQUES; PROCESSING ELEMENTS; PROCESSING POWER; PROCESSOR-IN-MEMORY;

SILICON ON INSULATOR TECHNOLOGY; THREE DIMENSIONAL;

RANDOM ACCESS STORAGE;

EID: 84893751635     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. D. G. Elliott, M. Stumm, W. M. Snelgrove, C. Cojocaru and R. McKenzie, "Computational RAM: implementing processors in memory", IEEE Design and Test of Comp., pp. 32-41, January-March 1999.
2. C.T. Chuang, P. F. Lu and C. J. Anderson, "SOI for digital CMOS VLSI: design considerations and advances", Proc. of the IEEE, vol. 86, n. 4, pp. 689-720, April 1998.
3. J. A. Burns et al, "3D circuit integration technology for multiproject fabrication", MIT Lincoln Laboratory, May 2001, DARPA PI Meeting.
4. J. A. Burns et al, "Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip", in Proc. IEEE Int. Solid-State Circuits Conf., pp. 268-269, 453, February 2001.
5. K. Kioi et al, "Design and implementation of a 3D-LSI image sensing processor", IEEE J. of Solid-State Circuits, vol. 27, n. 8, pp. 1130-1140, August 1992.
6. Y. Akasaka, "Three-dimensional IC trends", Proc. of the IEEE, vol. 74, n. 12, pp. 1703-1714, Decemeber 1986.
7. J. Childers et al, "SVP: serial video processor", in Proc. IEEE Cust. Integ. Circ. Conf., pp. 17.3/1-17.3/4, May 1990.
8. J. C. Gealow and C. G. Sodini, "A pixel-parallel image processor using logic pitch-matched to dynamic memory", IEEE J. of Solid-State Circuits, vol. 34, n. 6, pp. 831-839, June 1999.
9. R. J. Sung, J. C. Koob, T. L. Brandon, D. G. Elliott and B.F. Cockburn, "Design of an embedded fully-depleted SOI SRAM", in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing, pp. 13-18, August 2001.
10. T. Miwa, H. Yamada, Y. Hirota, T. Satoh and H. Hara, "A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies", IEEE J. of Solid-State Circuits, vol. 31, n. 11, pp. 1601-1609, November 1996.
11. J. G. Fossum and S. Krishnan, "Physical modeling needed for reliable SOI circuit design", IEICE Trans. on Electron., vol. E80-C, n. 3, pp. 388-393, March 1997.