Automatic datapath tile placement and routing

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2001, Pages 552-559

  Serdar, Tatjana ^a   Sechen, Carl ^a  

^a UNIVERSITY OF WASHINGTON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA PATHS; GLOBAL PLACEMENTS; PLACEMENT AND ROUTING; PLACEMENT PROCESS; TRANSISTOR LEVEL;

EXHIBITIONS; FORESTRY; SIMULATED ANNEALING;

DESIGN;

EID: 84893683652     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2001.915078     Document Type: Conference Paper

References (15)

1. th ACM/IEEE DAC, 1999, pp. 268-273.
2. Y. Pang, C. K. Cheng and T. Yoshimura, "An Enhanced Perturbing Algorithm for Floorplan Design Using the Otree Representation", Proc. 1SPD, 2000, pp. 168-173.
3. H. Murata, K. Fujiyoshi, S. Nakatake and Y. Kajitani, "Rectangle-Packing-Based Module Placement", Proc. ICCAD, 1995, pp. 472-479.
4. H. Murata, K. Fujiyoshi and M. Kaneko, "VLSI/PCB Placement with Obstacles Based on Sequence-Pair", IEEE Trans. On Computer-Added Design, vol. 17, pp. 60-68, 1998.
5. J. Xu, P. N. Guo and C. K. Cheng, "Rectilinear Block Placement using Sequence Pair", Proc. International Symposium on Physical Design, 1998, pp. 173-178.
6. M. Z. W. Kang and W. W. M. Dai, "Topology Constrained Rectilinear Block Packing", Proc. International Symposium on Physical Design, 1998, pp. 179-186.
7. K. Fujiyoshi and H. Murata, "Arbitrary Convex and Concave Rectilinear Block Packing", IEEE Trans. Computer-Added Design, vol. 19, no. 2, 2000, pp. 224-233.
8. M. Z. Kang and W. W. M. Dai, "Arbitrary Rectilinear Block Packing Based on Sequence Pair", Proc. ICCAD, 1998, pp. 259-266.
9. S. Nakatake, K. Fujiyoshi, H. Murata and Y. Kajitani, "Module Placement on BSG Structure and VLSI Layout Application", Proc. ICCAD, 1996, pp. 484-491.
10. M. Kang and W. W. M. Dai, "General Floorplanning with L-shaped, T-shaped and Soft Blocks Based on BSG Structure", Proc. ASP-DAC, 1997, pp. 265-270.
11. S. Nakatake, K. Fujiyoshi, H. Murata and Y. Kajitani, "Module Packing based on the BSG-structure and 1C Layout Application", IEEE Trans. Computer-Added Design, vol. 17, no. 6, 1998, pp. 519-530.
12. K. Sakanushi, S. Nakatake and Y. Kajitani, "The Multi-BSG: Stochastic Approach to an Optimum Packing of Convex-Rectilinear Blocks", Proc. ICCAD, 1998, pp. 267-274.
13. D. Vahia and M. Ciesielski, "Transistor Level Placement for Full Custom Datapath Cell Design", Proc. ISPD, 1999., pp. 158-163.
14. S. Askar and M. Ciesielski, "Analytical Approach to Custom Datapath Design", Proc. ICCAD, 1999, pp. 98-101.
15. T. Serdar and C. Sechen, "AKORD: Transistor Level and Mixed Transistor/Gate Level Placement Tool for Digital Datapaths", Proc. ICCAD, 1999, pp. 91-97