Optimizing dominant time constant in rc circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 2, 1998, Pages 110-125

  Vandenberghe, Lieven ^a   Boyd, Stephen ^a   Gamal, Abbas El ^b  

^a University of California   (United States)

^b Stanford University   (United States)

Author keywords

Circuit optimization; Circuit topology; Clocks; Crosstalk; Delay effects; Dominant time constant; Integrated circuit interconnections; Nonlinear programming; Rc circuits; Semidefinite programming

Indexed keywords

CAPACITORS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC WIRING; NONLINEAR PROGRAMMING; PASSIVE NETWORKS; RESISTORS; TIMING CIRCUITS;

DOMINANT TIME CONSTANT; INTERIOR POINT METHODS; RESISTOR CAPACITOR (RC) CIRCUITS; SEMIDEFINITE PROGRAMMING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0032001494     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.681261     Document Type: Article

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