An analog online clustering circuit in 130nm CMOS

Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013

Volumn , Issue , 2013, Pages 177-180

  Lu, Junjie ^a   Young, Steven ^a   Arel, Itamar ^a   Holleman, Jeremy ^a  

^a UNIVERSITY OF TENNESSEE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG COMPUTATION; DIGITAL COUNTERPARTS; DISTANCE COMPUTATION; ONLINE-CLUSTERING; ROBUST LEARNING ALGORITHM; STANDARD CMOS PROCESS; STATISTICAL PARAMETERS; VECTOR CLASSIFICATIONS;

ANALOG COMPUTERS; BANDPASS FILTERS; CMOS INTEGRATED CIRCUITS; ENERGY EFFICIENCY;

ANALOG CIRCUITS;

EID: 84893524268     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2013.6691011     Document Type: Conference Paper

References (12)

1. S. Chakrabartty and G. Cauwenberghs, "Sub-microwatt analog VLSI trainable pattern classifier," IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 1169-1179, May 2007.
2. R. Chawla, A. Bandyopadhyay, V. Srinivasan and P. Hasler, "A 531nW/MHz, 128x32 current-mode programmable analog vector-matrix multiplier with over two decades of linearity," in Proc. IEEE Custom Integr. Circuits Conf. (CICC), Oct. 2004.
3. J. Lubkin and G. Cauwenberghs, "A micropower learning vector quantizer for parallel analog-to-digital data compression," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 1998, pp. 58-61.
4. K. Kang and T. Shibata, "An on-chip-trainable Gaussian-kernel analog support vector machine," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 7, pp. 1513-1524, Jul. 2010.
5. D. J. C. MacKay, Information Theory, Inference and Learning Algorithms, New York, NY, USA: Cambridge University Press, 2003.
6. R. Sarpeshkar, "Analog versus digital: extrapolating from electronics to neurobiology," Neural Comput., vol. 10, no. 7, pp. 1601-1638, Oct. 1998.
7. I. Arel, D. Rose and T. Karnowski, "A deep learning architecture comprising homogeneous cortical circuits for scalable spatiotemporal pattern inference," in Proc. NIPS 2009 Workshop on Deep Learning for Speech Recognition and Related Applications, Dec. 2009.
8. J. Lu and J. Holleman, "A floating-gate analog memory with bidirectional sigmoid updates in a standard digital process," in Proc. IEEE Int. Symp. Circuit Syst. (ISCAS), May 2013.
9. Z. Wang, "Novel pseudo RMS current converter for sinusoidal signals using a CMOS precision current rectifier," IEEE Trans. Instrum. Meas., vol. 39, no. 4, pp. 670-671, Aug. 1990.
10. B. Gilbert, "Translinear circuits: a proposed classification," Electron. Lett., vol. 11, no. 1, pp. 14-16, 1975.
11. J. Lazzaro, S. Ryckebusch, M. A. Mahowald and C. Mead, "Winner-takeall networks of O(n) complexity," in Advances in Neural Information Processing Systems 1, D. S. Touretzky, Ed. San Mateo, CA: Morgan Kauffman, 1989, pp. 703-711.
12. S. Young, I. Arel, T. Karnowski and D. Rose, "A fast and stable incremental clustering algorithm," in Proc. 7th International Conference on Information Technology, Apr. 2010.