-
1
-
-
0035051733
-
A cmos programmable analog memory-cell array using floating-gate circuits
-
Jan.
-
R. R. Harrison, J. A. Bragg, P. Hasler, B. A. Minch and S. P. Deweerth, "A CMOS programmable analog memory-cell array using floating-gate circuits," IEEE Trans. Circuits Syst.II, Analog Digit. Signal Process., vol. 48, no. 1, pp. 4-11, Jan. 2001.
-
(2001)
IEEE Trans. Circuits Syst.II, Analog Digit. Signal Process.
, vol.48
, Issue.1
, pp. 4-11
-
-
Harrison, R.R.1
Bragg, J.A.2
Hasler, P.3
Minch, B.A.4
Deweerth, S.P.5
-
2
-
-
36348956891
-
An analog programmable multidimensional radial basis function based classifier
-
Oct.
-
S. Peng, P. Hasler and D. V. Anderson, "An analog programmable multidimensional radial basis function based classifier," IEEE Trans Circuits and Syst. I, Reg Papers, vol. 54, no. 10, pp. 2148-2158, Oct. 2007.
-
(2007)
IEEE Trans Circuits and Syst. I, Reg Papers
, vol.54
, Issue.10
, pp. 2148-2158
-
-
Peng, S.1
Hasler, P.2
Anderson, D.V.3
-
3
-
-
20144384900
-
An analog floating-gate node for supervised learning
-
May
-
P. Hasler and J. Dugger, "An analog floating-gate node for supervised learning," IEEE Trans Circuits and Syst. I, Reg Papers, vol. 52, no. 5, pp. 834-845, May 2005.
-
(2005)
IEEE Trans Circuits and Syst. I, Reg Papers
, vol.52
, Issue.5
, pp. 834-845
-
-
Hasler, P.1
Dugger, J.2
-
4
-
-
3042822110
-
A 19.2 gops mixedsignal filter with floating-gate adaptation
-
July
-
M. Figueroa, S. Bridges, D. Hsu and C. Diorio, "A 19.2 GOPS mixedsignal filter with floating-gate adaptation," IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1196-1201, July 2004.
-
(2004)
IEEE J. Solid-State Circuits
, vol.39
, Issue.7
, pp. 1196-1201
-
-
Figueroa, M.1
Bridges, S.2
Hsu, D.3
Diorio, C.4
-
5
-
-
0026173510
-
Review of carrier injection in the silicon/silicon-dioxide system
-
Jun.
-
J. J. Sanchez and T. A. DeMassa, "Review of carrier injection in the silicon/silicon-dioxide system," IEE Proc. G-Circuits, Devices Systems, vol. 138, no. 3, pp. 377-389, Jun. 1991.
-
(1991)
IEE Proc. G-Circuits, Devices Systems
, vol.138
, Issue.3
, pp. 377-389
-
-
Sanchez, J.J.1
Demassa, T.A.2
-
6
-
-
0033874491
-
A p-channel mos synapse transistor with self-convergent memory writes
-
Feb.
-
C. Diorio, "A p-channel MOS synapse transistor with self-convergent memory writes," IEEE Trans. Electron Dev., vol. 47, no. 2, pp. 464-472, Feb. 2000.
-
(2000)
IEEE Trans. Electron Dev.
, vol.47
, Issue.2
, pp. 464-472
-
-
Diorio, C.1
-
7
-
-
0036294819
-
A simulation model for floating-gate mos synapse transistors
-
May
-
K. Rahimi, C. Diorio, C. Hernandez and M. D. Brockhausen, "A simulation model for floating-gate MOS synapse transistors," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May 2002, vol. 2, pp.532-535.
-
(2002)
Proc. IEEE Int. Symp. Circuits Syst. (ISCAS)
, vol.2
, pp. 532-535
-
-
Rahimi, K.1
Diorio, C.2
Hernandez, C.3
Brockhausen, M.D.4
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