Energy-efficient recognition and mining processor using scalable effort design

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2013, Pages

  Chippa, Vinay K ^a   Jayakumar, Hrishikesh ^a   Mohapatra, Debabrata ^a   Roy, Kaushik ^a   Raghunathan, Anand ^a  

^a Purdue University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL EFFICIENCY; DESIGN; ENERGY EFFICIENCY; ENERGY UTILIZATION; INTEGRATED CIRCUITS;

COMPUTATIONAL KERNELS; CROSS-LAYER APPROACH; ENERGY EFFICIENT; INTERCONNECT NETWORKS; MATRIX VECTOR MULTIPLICATION; PROCESSING ELEMENTS; SCALING MECHANISM; STREAMING MEMORY;

COMPUTER ARCHITECTURE;

EID: 84892644983     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2013.6658433     Document Type: Conference Paper

References (10)

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4. S. Lee et al. A 345mw heterogeneous many-core processor with an intelligent inference engine for robust object recognition. In Proc. ISSCC, pages 332-333, 2010.
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7. V.K. Chippa, D. Mohapatra, A.Raghunathan, K. Roy, and S.T. Chakradhar. Scalable effort hardware design: Exploiting algorithmic resilience for energy efficiency. In Proc. DAC, 2010.
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10. Debabrata Mohapatra et al. Design of Voltage Scalable Metafunctions for Multimedia, Recoginition and Mining Applications. In Proc. DATE, pages 950-955, 2011.