A low-power digital filter IC via soft DSP

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2001, Pages 309-312

  Hegde, R ^a   Shanbhag, N R ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; DIGITAL FILTERS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; SIGNAL TO NOISE RATIO;

ALGORITHMIC NOISE TOLERANCE; SOFT DIGITAL SIGNAL PROCESSORS; VOLTAGE OVERSCALING;

DIGITAL SIGNAL PROCESSING;

EID: 0034829115     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Minimizing power consumption in digital CMOS circuits
2. Supply and threshold voltage scaling for low power CMOS
3. Energy efficient filtering using adaptive precision and variable voltage
4. Energy efficient signal processing via algorithmic noise-tolerance