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Volumn , Issue , 2005, Pages 55-84

Global interconnect analysis

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EID: 84891420713     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/1-4020-7836-6_3     Document Type: Chapter
Times cited : (1)

References (30)
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    • 0034474752 scopus 로고    scopus 로고
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    • Shepard, K.L.1    Sitaram, D.2    Zheng, Y.3
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    • A simple formula for the estimation of the capacitance of two-dimensional interconnects in VLSI circuits
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    • Yuan, C.P.1    Trick, T.N.2
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    • 0041297627 scopus 로고    scopus 로고
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    • L. R. Zheng, D. Pamunuwa, and H. Tenhunen. Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep sub-micron VLSI design. In Proceedings of European Solid-State Circuit Conference, pages 324-327, 2000.
    • (2000) Proceedings of European Solid-State Circuit Conference , pp. 324-327
    • Zheng, L.R.1    Pamunuwa, D.2    Tenhunen, H.3
  • 8
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    • January
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    • August
    • T. Sakurai. Approximation of wiring delay in MOSFET LSI. IEEE Journal of Solid-State Circuits, 18:418-426, August 1983.
    • (1983) IEEE Journal of Solid-State Circuits , vol.18 , pp. 418-426
    • Sakurai, T.1
  • 15
    • 0033698637 scopus 로고    scopus 로고
    • On switch factor based analysis of coupled RC interconnects
    • June
    • A. B. Kahng, S. Muddu, and E. Sarto. On switch factor based analysis of coupled RC interconnects. In Proceedings of DAC, pages 79-84, June 2000.
    • (2000) Proceedings of DAC , pp. 79-84
    • Kahng, A.B.1    Muddu, S.2    Sarto, E.3
  • 16
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    • On a pin versus block relationship for partitions of logic graphs
    • December
    • B. S. Landman and R. L. Russo. On a pin versus block relationship for partitions of logic graphs. IEEE Transactions on Computers, C20(12):1469-1479, December 1971.
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  • 17
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.