Power-management features of R-mobile U2, an integrated application processor and baseband processor

IEEE Micro

Volumn 33, Issue 6, 2013, Pages 26-36

  Fukuoka, Kazuki ^a   Maeda, Noriaki ^a   Nii, Koji ^a   Fujigaya, Masaki ^b   Sakamoto, Noriaki ^b   Koike, Takao ^b   Irita, Takahiro ^b   Wakahara, Kohei ^b   Matsuyama, Tsugio ^b   Hasegawa, Keiji ^b   Saito, Toshiharu ^b   Fukuda, Akira ^b   Teranishi, Kaname ^b   Kataoka, Takeshi ^b   Hattori, Toshihiro ^b  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b Renesas Mobile ^*  (Japan)

Author keywords

28 nm technology; Application and LTE capable baseband processor; Dual standby mode SRAM; Maximum power control; Power switch

Indexed keywords

APPLICATION PROCESSORS; BASEBAND PROCESSORS; INTEGRATED APPLICATIONS; MAXIMUM POWER; POWER MANAGEMENTS; POWER SWITCHES; STATIC RAMS; TRIPLE-BAND;

NANOTECHNOLOGY;

WIRELESS TELECOMMUNICATION SYSTEMS;

EID: 84890915477     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2013.109     Document Type: Article

References (8)

1. M. Fujigaya et al., "A 28 nm High-k Metal- Gate Single-Chip Communications Processor with 1.5 GHz Dual-Core Application Processor and LTE/HSPA+-Capable Baseband Processor," Proc. IEEE Int'l Solid-State Circuits Conf., IEEE CS, 2013, pp. 156-157.
2. MSM8960 data sheet, Qualcomm, 15 Oct. 2012; www.qualcomm.co.jp/sites/ default/files/common/products-services/ snapdragon specs 9-12.pdf.
3. M. Shirasaki et al., "A 45 nm Single-Chip Application-and-Baseband Processor Using an Intermittent Operation Technique," Proc. IEEE Int'l Solid-State Circuits Conf., IEEE CS, 2009, pp. 156-157.
4. M. Naruse et al., "A 65 nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IPMMU," Proc. IEEE Int'l Solid-State Circuits Conf., IEEE CS, 2008, pp. 260-261.
5. K. Fukuoka et al., "A 123 lW Standby Power Technique with EM-Tolerant 1.8 V I/O NMOS Power Switch in 28 nmHKMG Technology," Proc. IEEE Custom Integrated Circuits Conf., IEEE CS, 2012, doi:10.1109/ CICC.2012.6330708.
6. P. Chidambaram et al., "Cost Effective 28 nm LP SoC Technology Optimized with Circuit/Device/Process Co-design for Smart Mobile Devices," Proc. IEEE Int'l Electron Devices Meeting, IEEE CS, 2010, pp. 27.3.1-27.3.4.
7. K. Fukuoka et al., "A 1.92 us-Wake-Up Time Thick-Gate-Oxide Power Switch Technique for Ultra Low-Power Single-Chip Mobile Processors," IEEE Symp. VLSI Circuits, IEEE CS, 2007, pp. 128-129. (Pubitemid 351306593)
8. N.Maeda et al., "A 0.14 lA Standby Leakage 23 Kb Embedded SRAM with Low Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS," IEEE Symp. VLSI Circuits, IEEE CS, 2012, pp. 58-59.