Cost effective 28nm LP SoC technology optimized with circuit/device/process co-design for smart mobile devices

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2010, Pages

  Chidambaram, P R ^a   Gan, C ^a   Sengupta, S ^a   Ge, L ^a   Chen, Y ^a   Yang, S ^a   Liu, P ^a   Wang, J ^a   Yang, M ^a   Teng, C ^a   Du, Y ^a   Patel, P ^a   Kamal, P ^a   Bucki, R ^a   Vang, F ^a   Datta, A ^a   Bellur, K ^a   Yoon, S ^a   Chen, N ^a   Thean, A ^a   Han, M ^a   Terzioglu, E ^a   Zhang, X ^a   Fischer, J ^a   Sani, M ^a   Flederbach, B ^a   Yeap, Geoffrey ^a   more..

^a QUALCOMM INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CO-DESIGN APPROACH; CO-DESIGNS; COST EFFECTIVE; DESIGN RULES; DESIGN STRATEGIES; GATE DENSITY; MANUFACTURING FLOW; OPTIMAL POWER; TECHNOLOGY NODES;

COST EFFECTIVENESS; ELECTRON DEVICES; MOBILE DEVICES; OPTIMIZATION;

DESIGN;

EID: 79951828922     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2010.5703432     Document Type: Conference Paper

References (3)

1. G. Yeap, VLSI Tech 2010 p. 223
2. PR Chidambaram et al, VLSI Tech 2004 p. 46
3. SH. Wu et al., VLSI Tech 2009 p. 210