A 65nm single-chip application and dual-mode baseband processor with partial clock activation and IP-MMU

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 259-261

  Naruse, Masao ^a   Kamei, Tatsuya ^a   Hattori, Toshihiro ^a   Irita, Takahiro ^a   Nitta, Kenichi ^a   Koike, Takao ^a   Yoshioka, Shinichi ^a   Ohno, Koji ^a   Saigusa, Masahito ^b   Sakata, Minoru ^c   Kodama, Yukio ^d   Arai, Yuji ^e   Komuro, Teruyoshi ^f  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b NTT DOCOMO   (Japan)

^c FUJITSU LABORATORIES LTD   (Japan)

^d MITSUBISHI ELECTRIC CORPORATION   (Japan)

^e SHARP CORPORATION   (Japan)

^f SONY CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL ACTIVATION; CLOCKS; MEMORY MANAGEMENT UNITS; MOBILE TELECOMMUNICATION SYSTEMS; VIDEO SIGNAL PROCESSING; VIRTUAL ADDRESSES;

BASEBAND PROCESSORS; CLOCK ACTIVATION; DUAL MODES; EXTERNAL MEMORY; POWER DOMAIN; SINGLE CHIPS; VIDEO PROCESSING; VIRTUAL MEMORY;

PHYSICAL ADDRESSES;

EID: 49549101621     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523156     Document Type: Conference Paper

References (2)

1. T. Hattori, et al., "A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor,"ISSCC Dig. Tech. Papers, pp. 542-543, Feb. 2006.
2. M. Ito, et al., "A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vth CMOS," ISSCC Dig. Tech. Papers, pp. 274-275, Feb. 2006.