A 45nm single-chip application-and-baseband processor using an intermittent operation technique

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 156-158

  Shirasaki, Motoyasu ^a   Miyazaki, Yusaku ^a   Hoshaku, Masahiro ^a   Yamamoto, Hiroo ^a   Ogawa, Sachio ^a   Arimura, Takuya ^a   Hirai, Hiroshi ^a   Iizuka, Yasuo ^a   Sekibe, Tsutomu ^a   Nishida, Yoichi ^a   Ishioka, Toshiyuki ^a   Michiyama, Junji ^a  

^a Panasonic Tokyo   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349297495     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977355     Document Type: Conference Paper

References (4)

1. M. Naruse, et al., "A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU," ISSCC Dig. Tech. Papers, pp. 260- 262, Feb. 2008.
2. G. Gammie, et al., "A 45nm Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques," ISSCC Dig. Tech. Papers, pp. 258-259, Feb. 2008.
3. M. Nakajima, et al., "Instruction Parallel Processor (IPP) Architecture on Panasonic Integrated Platform for Digital CE," Spring Processor Forum, May 2005.
4. M. Sumita, et al., "Mixed Body-Bias Techniques with Fixed Vt and Ids Generation Circuits," ISSCC Dig. Tech. Papers, pp.158-159, Feb. 2004.