Layout-aware analog system synthesis based on symbolic layout description and combined block parameter exploration, placement and global routing

Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI

Volumn 2003-January, Issue , 2003, Pages 266-271

  Tang, Hua ^a   Zhang, Hui ^a   Doboli, Alex ^a  

^a Stony Brook University   (United States)

Author keywords

Circuit simulation; Circuit synthesis; Design automation; Design optimization; Integrated circuit interconnections; Laboratories; Routing; Signal synthesis; SPICE; Wire

Indexed keywords

CIRCUIT SIMULATION; COMPUTER AIDED DESIGN; LABORATORIES; SPICE; VLSI CIRCUITS; WIRE;

CIRCUIT SYNTHESIS; DESIGN AUTOMATIONS; DESIGN OPTIMIZATION; INTEGRATED CIRCUIT INTERCONNECTIONS; ROUTING; SIGNAL SYNTHESIS;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84889779638     PISSN: 21593469     EISSN: 21593477     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2003.1183495     Document Type: Conference Paper

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