Module placement for analog layout using the sequence-pair representation

Proceedings - Design Automation Conference

Volumn , Issue , 1999, Pages 274-279

  Balasa, Florin ^a   Lampaert, Koen ^a  

^a Rockwell Semiconductor Systems   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT LAYOUT; SIMULATED ANNEALING;

ANALOG LAYOUTS; GELLAT-JEPSEN SPATIAL REPRESENTATIONS; SEQUENCE-PAIR REPRESENTATIONS;

MICROPROCESSOR CHIPS;

EID: 0032667120     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/309847.309930     Document Type: Conference Paper

References (14)