Modeling and implementation of an all digital phase-locked-loop for grid-voltage phase detection

IEEE Transactions on Industrial Informatics

Volumn 9, Issue 2, 2013, Pages 772-780

  Geng, Hua ^a   Sun, Jianbo ^b   Xiao, Shuai ^a   Yang, Geng ^a  

^a TSINGHUA UNIVERSITY   (China)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

All digital phase locked loop (ADPLL); Digital system modeling; Phase detection

Indexed keywords

ALL DIGITAL; DIGITAL CONTROLLERS; DIGITAL SYSTEM; LOW COST APPLICATIONS; PHASE DETECTION; PROPORTIONAL-INTEGRAL; SAMPLING FREQUENCIES; STEADY STATE ERRORS;

ELECTRICAL ENGINEERING; INDUSTRY;

PHASE LOCKED LOOPS;

EID: 84889243886     PISSN: 15513203     EISSN: None     Source Type: Journal    
DOI: 10.1109/TII.2012.2209666     Document Type: Article

References (26)

1. G.-C. Hsieh and J. Hung, "Phase-locked loop techniques. a survey," IEEE Ind. Electron., vol. 43, no. 6, pp. 609-615, Dec. 1996.
2. H. Geng, D. Xu, and B. Wu, "A novel hardware-based all-digital phase-locked loop applied to grid-connected power converters," IEEE Ind. Electron., vol. 58, no. 5, pp. 1737-1745, May 2011.
3. C. Xia, M. Wang, Z. Song, and T. Liu, "Robust model predictive current control of three-phase voltage source pwm rectifier with online disturbance observation," IEEE Ind. Inf., vol. PP, no. 99, p. 1, 2012.
4. H. Geng, G. Yang, D. Xu, and B. Wu, "Unified power control for pmsg-based wecs operating under different grid conditions," IEEE Trans. Energy Conv., vol. 26, no. 3, pp. 822-830, Sept. 2011.
5. M. Cichowlas, M. Malinowski, M. P. Kazmierkowski, D. L. Sobczuk, P. Rodriguez, and J. Pou, "Active filtering function of three-phase pwm boost rectifier under different line voltage conditions," IEEE Ind. Electron., vol. 52, no. 2, pp. 410-419, 2005.
6. P. Rodriguez, A. V. Timbus, R. Teodorescu, M. Liserre, and F. Blaabjerg, "Flexible active power control of distributed power generation systems during grid faults," IEEE Ind. Electron., vol. 54, no. 5, pp. 2583-2592, 2007.
7. T. Thacker, D. Boroyevich, R. Burgos, and F. Wang, "Phase-locked loop noise reduction via phase detector implementation for single-phase systems," IEEE Ind. Electron., vol. 58, no. 6, pp. 2482-2490, June 2011.
8. F. Freijedo, A. Yepes, O. Lopez, P. Fernandez-Comesana, and J. Doval-Gandoy, "An optimized implementation of phase locked loops for grid applications," IEEE Trans. Instrum. Meas., vol. 60, no. 9, pp. 3110-3119, Sept. 2011.
9. S. Golestan, M. Monfared, F. Freijedo, and J. Guerrero, "Dynamics assessment of advanced single-phase pll structures," IEEE Ind. Electron., vol. PP, no. 99, p. 1, 2012.
10. S. Golestan, M. Monfared, F. Freijedo, and J. Guerrero, "Design and tuning of a modified power-based pll for single-phase grid-connected power conditioning systems," IEEE Trans. Power Electron., vol. 27, no. 8, pp. 3639-3650, Aug. 2012.
11. N. Ama, F. Martinz, L. Matakas, Jr, and F. Junior, "Phase locked loop based on selective harmonics elimination for utility applications," IEEE Trans. Power Electron., to be published.
12. F. Liccardo, P. Marino, and G. Raimondo, "Robust and fast three-phase pll tracking system," IEEE Ind. Electron., vol. 58, no. 1, pp. 221-231, Jan. 2011.
13. M. Perez, J. Espinoza, L. Moran, M. Torres, and E. Araya, "A robust phase-locked loop algorithm to synchronize static-power converters with polluted ac systems," IEEE Ind. Electron., vol. 55, no. 5, pp. 2185-2192, May 2008.
14. P. Rodriguez, J. Pou, J. Bergas, J. I. Candela, R. P. Burgos, and D. Boroyevich, "Decoupled double synchronous reference frame pll for power converters control," IEEE Trans. Power Electron., vol. 22, no. 2, pp. 584-592, Feb., 2007.
15. H. de Souza, F. Bradaschia, F. Neves, M. Cavalcanti, G. Azevedo, and J. de Arruda, "A method for extracting the fundamental-frequency positive-sequence voltage vector based on simple mathematical transformations," IEEE Ind. Electron., vol. 56, no. 5, pp. 1539-1547, May 2009.
16. G. Escobar, M. Martinez-Montejano, A. Valdez, P. Martinez, and M. Hernandez-Gomez, "Fixed-reference-frame phase-locked loop for grid synchronization under unbalanced operation," IEEE Ind. Electron., vol. 58, no. 5, pp. 1943-1951, May 2011.
17. S. Chung, H. Shin, and H. Lee, "Precision control of single-phase pwm inverter using pll compensation," IEE Proc. Electric Power Appl., vol. 152, no. 2, pp. 429-436, March 2005.
18. S. Shinnaka, "A novel fast-tracking d-estimation method for single-phase signals," IEEE Trans. Power Electron., vol. 26, no. 4, pp. 1081-1088, Apr. 2011.
19. T. J. Rey, W. C. Lindsey, and C. M. Chie, "Comments on "a survey of digital phase locked loops"," Proc. IEEE, vol. 70, no. 2, pp. 201-202, 1982.
20. D. Xu, Y. W. Li, and B. Wu, "Direct pwm synchronization using an all digital phase-locked loop for high power grid-interfacing converters," in Proc. APEC 2007, pp. 901-906.
21. M. Yahara, H. Sasaki, K. Fujimoto, and H. Sasaki, "All digital dividing ratio changeable type phase-locked loop with a wide lock-in range," Electron. Commun. Jpn. I - Commun., vol. 88, no. 2, pp. 41-49, 2005.
22. D. G. Troha, "Digital Phase-Locked Loop Design Using Sn54/74Ls297," Texas Instruments Incorporated, USA, Texas Instruments Application Note, Mar. 1997.
23. S. Walters and T. Troudet, "Digital phase-locked loop with jitter bounded," IEEE Trans. Circuits Syst., vol. 36, no. 7, pp. 980-987, Jul. 1989.
24. S. Pavljasevic and F. Dawson, "Phase synchronization using zero crossing sampling digital phase-locked loop," in Proc. PCC Osaka, 2002, vol. 2, pp. 665-670.
25. N.-G. Kim and I.-J. Ha, "Design of adpll for both large lock-in range and good tracking performance," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 9, pp. 1192-1204, Sep. 1999.
26. H. Geng, D. Xu, B. Wu, and G. Yang, "Active islanding detection for inverter-based distributed generation systems with power control interface," IEEE Trans. Energy Conv., vol. 26, no. 4, pp. 1063-1072, Dec. 2011.