A novel hardware-based all-digital phase-locked loop applied to grid-connected power converters

IEEE Transactions on Industrial Electronics

Volumn 58, Issue 5, 2011, Pages 1737-1745

  Geng, Hua ^a   Xu, Dewei ^b   Wu, Bin ^b  

^a TSINGHUA UNIVERSITY   (China)

^b RYERSON UNIVERSITY   (Canada)

Author keywords

All digital phase locked loop (ADPLL); grid connected power converters; positive and negative sequence separation

Indexed keywords

ALL DIGITAL PHASE LOCKED LOOP; CLOCK FREQUENCY; DIGITAL CONTROLLERS; GRID DISTURBANCE; GRID INTERFACES; GRID VOLTAGE; GRID-CONNECTED; NOVEL HARDWARE; OUTPUT PHASE; PARAMETER DEPENDENCE; PHASE ANGLES; POSITIVE- AND NEGATIVE-SEQUENCE SEPARATION; PULL-IN; PULSE JITTER; SMALL SIGNAL MODEL; SYSTEM OPERATION; UTILITY VOLTAGES; VOLTAGE SENSOR; VOLTAGE ZERO-CROSSINGS;

HETEROJUNCTION BIPOLAR TRANSISTORS; JITTER; PHASE INTERFACES; POWER CONVERTERS;

PHASE LOCKED LOOPS;

EID: 79954516747     PISSN: 02780046     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIE.2010.2053338     Document Type: Article

References (27)

1. P. Rodriguez, J. Pou, J. Bergas, J. I. Candela, R. P. Burgos, and D. Boroyevich, "Decoupled double synchronous reference frame PLL for power converters control," IEEE Trans. Power Electron., vol. 22, no. 2, pp. 584-592, Mar. 2007. (Pubitemid 46523183)
2. M. Cichowlas, M. Malinowski, M. P. Kazmierkowski, D. L. Sobczuk, P. Rodriguez, and J. Pou, "Active filtering function of three-phase PWM boost rectifier under different line voltage conditions," IEEE Trans. Ind. Electron., vol. 52, no. 2, pp. 410-419, Apr. 2005. (Pubitemid 40573524)
3. R.M. S. Filho, P. F. Seixas, P. C. Cortizo, L. A. B. Torres, and A. F. Souza, "Comparison of three single-phase PLL algorithms for UPS applications," IEEE Trans. Ind. Electron., vol. 55, no. 8, pp. 2923-2932, Aug. 2008.
4. P. Rodriguez, A. V. Timbus, R. Teodorescu, M. Liserre, and F. Blaabjerg, "Flexible active power control of distributed power generation systems during grid faults," IEEE Trans. Ind. Electron., vol. 54, no. 5, pp. 2583-2592, Oct. 2007.
5. J. R. Espinoza and G. Joos, "State variable decoupling and power flow control in PWM current-source rectifiers," IEEE Trans. Ind. Electron., vol. 45, no. 1, pp. 78-87, Feb. 1998. (Pubitemid 128739742)
6. L. Asiminoaei, F. Blaabjerg, and S. Hansen, "Detection is key-Harmonic detection methods for active power filter applications," IEEE Ind. Appl. Mag., vol. 13, no. 4, pp. 22-33, Jul./Aug. 2007. (Pubitemid 47287340)
7. T. J. Rey, W. C. Lindsey, and C. M. Chie, "Comments on 'A survey of digital phase locked loops'," Proc. IEEE, vol. 70, no. 2, pp. 201-202, Feb. 1982.
8. D. Xu, Y. W. Li, and B. Wu, "Direct PWM synchronization using an all digital phase-locked loop for high power grid-interfacing converters," in Proc. 22nd Annu. IEEE APEC, Mar. 1-25, 2007, pp. 901-906.
9. M. Yahara, H. Sasaki, K. Fujimoto, and H. Sasaki, "All digital dividing ratio changeable type phase-locked loop with a wide lock-in range," Electron. Commun. Jpn. Part I-Commun., vol. 88, no. 2, pp. 41-49, 2005.
10. V. Kaura and V. Blasko, "Operation of a phase locked loop system under distorted utility conditions," IEEE Trans. Ind. Appl., vol. 33, no. 1, pp. 58-63, Jan./Feb. 1997.
11. L. Arruda, S. Silva, and B. Filho, "PLL structures for utility connected systems," in Conf. Rec. 36th IEEE IAS Annu. Meeting, Sep. 4-Oct. 2001, vol. 4, pp. 2655-2660. (Pubitemid 33058699)
12. H. de Souza, F. Bradaschia, F. Neves, M. Cavalcanti, G. Azevedo, and J. de Arruda, "A method for extracting the fundamental-frequency positive-sequence voltage vector based on simple mathematical transformations," IEEE Trans. Ind. Electron., vol. 56, no. 5, pp. 1539-1547, May 2009.
13. G. Saccomando and J. Svensson, "Transient operation of gridconnected voltage source converter under unbalanced voltage conditions," in Conf. Rec. 36th IEEE IAS Annu. Meeting, Sep.-Oct. 4, 2001, vol. 4, pp. 2419-2424. (Pubitemid 33058666)
14. Y. Srinivasa Rao and M. Chandorkar, "Real-time electrical load emulator using optimal feedback control technique," IEEE Trans. Ind. Electron., vol. 57, no. 4, pp. 1217-1225, Apr. 2010.
15. Y. W. Li, B. Wu, D. Xu, and N. R. Zargari, "Space vector sequence investigation and synchronization methods for active front-end rectifiers in high-power current-source drives," IEEE Trans. Ind. Electron., vol. 55, no. 3, pp. 1022-1034, Mar. 2008. (Pubitemid 351447545)
16. D. G. Troha, Digital Phase-Locked Loop Design Using SN54/74LS297. Dallas, TX: Texas Instruments Inc., Mar. 1997.
17. N.-G. Kim and I.-J. Ha, "Design of ADPLL for both large lock-in range and good tracking performance," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 9, pp. 1192-1204, Sep. 1999. (Pubitemid 30542633)
18. S. Walters and T. Troudet, "Digital phase-locked loop with jitter bounded," IEEE Trans. Circuits Syst., vol. 36, no. 7, pp. 980-987, Jul. 1989.
19. S. Pavljasevic and F. Dawson, "Phase synchronization using zero crossing sampling digital phase-locked loop," in Proc. PCC Osaka, 2002, vol. 2, pp. 665-670.
20. J. Carrasco, L. Franquelo, J. Bialasiewicz, E. Galvan, R. Guisado, M. Prats, J. Leon, and N. Moreno-Alfonso, "Power-electronic systems for the grid integration of renewable energy sources: A survey," IEEE Trans. Ind. Electron., vol. 53, no. 4, pp. 1002-1016, Jun. 2006. (Pubitemid 44263711)
21. Grid Code-High and Extra High Voltage, E.ON Netz GmbH, Zurich, Switzerland, 2006, Tech. Rep. [Online]. Available: http://www. eon-netz.com/Ressources/downloads/ENENARHS2006eng.pdf
22. H.-S. Song and K. Nam, "Dual current control scheme for PWM converter under unbalanced input voltage conditions," IEEE Trans. Ind. Electron., vol. 46, no. 5, pp. 953-959, Oct. 1999. (Pubitemid 30524489)
23. F. Blaabjerg, R. Teodorescu, M. Liserre, and A. Timbus, "Overview of control and grid synchronization for distributed power generation systems," IEEE Trans. Ind. Electron., vol. 53, no. 5, pp. 1398-1409, Oct. 2006. (Pubitemid 44593490)
24. J. Svensson, M. Bongiorno, and A. Sannino, "Practical implementation of delayed signal cancellation method for phase-sequence separation," IEEE Trans. Power Del., vol. 22, no. 1, pp. 18-26, Jan. 2007. (Pubitemid 46566167)
25. S. Alepuz, S. Busquets-Monge, J. Bordonau, J. Martinez-Velasco, C. Silva, J. Pontt, and J. Rodriguez, "Control strategies based on symmetrical components for grid-connected converters under voltage dips," IEEE Trans. Ind. Electron., vol. 56, no. 6, pp. 2162-2173, Jun. 2009.
26. D. Yazdani, M. Mojiri, A. Bakhshai, and G. Joos, "A fast and accurate synchronization technique for extraction of symmetrical components," IEEE Trans. Power Electron., vol. 24, no. 3, pp. 674-684, Mar. 2009.
27. G. Saccomando, J. Svensson, and A. Sannino, "Improving voltage disturbance rejection for variable-speed wind turbines," IEEE Trans. Energy Convers., vol. 17, no. 3, pp. 422-428, Sep. 2002. (Pubitemid 35151680)