Non-linearity reduction technique for delay-locked delay-lines

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 4, Issue , 2001, Pages 430-433

  Fanucci, L ^b   Roncella, R ^a   Saletti, R ^a  

^a UNIVERSITY OF PISA   (Italy)

^b CNR   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALL DIGITAL; DELAY MISMATCH; DIGITAL CELLS; INDIVIDUAL CELLS; REDUCTION TECHNIQUES; SHUNT CAPACITORS;

CAPACITORS;

LOCKS (FASTENERS);

EID: 84888061224     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922265     Document Type: Conference Paper

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