Impact of power-supply noise on timing in high-frequency microprocessors

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn 2002-January, Issue , 2002, Pages 261-264

  Saint Laurent, Martin ^a   Swaminathan, Madhavan ^b  

^a INTEL CORPORATION   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS PACKAGING; MICROPROCESSOR CHIPS;

CLOCK FREQUENCY; DELAY MODELING; HIGH FREQUENCY HF; MODEL PARAMETERS; PAPER ANALYSIS; PENTIUM; POWER-SUPPLY NOISE; SYSTEM BOARDS;

ELECTRIC POWER SYSTEMS;

EID: 84886699132     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEP.2002.1057928     Document Type: Conference Paper

References (11)

1. "Physical and Predictive Models of Ultrathin Oxide Reliability in CMOS Devices and Circuits", James H. STATHIS, IEEE Transactions on Device and Materials Reliability, March 2001.
2. "A New Analytical Model of SRAM Cell Stability in Low-Voltage Operation", Tsutomo ICHIKAWA and Masayoshi SASAKI, IEEE Transactions on Electron Devices, January 1996.
3. "Fast Power Grid Simulation", Sani R. NASSIF, and Joseph N. KOZHAYA, ACMAEEE Design Automation Conference, 2000.
4. Nodel and analysis for combined package and on-chip power grid simulation R. PANDA et al. International Symposium on Low-Power Electronics and Design 2000
5. "Design and Analysis of Power Distribution Networks in PowerPCm Microprocessors", Abhijit DHARCHOUDHURY et al., Design Automation Conference, 1998.
6. "Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices", Yi-Min JIANG, and Kwang-Ting CHENG, Design Automation Conference, 1999.
7. "A Clock Distribution Network for Microprocessors", Phillip J. RESTLE et al. IEEE Journal of Solid-state Circuits, May 2001
8. "The Clock Distribution of the Power4 Microprocessor", Phillip J. RESTLE et al., IEEE International Solid-state Circuits Conference, 2002.
9. "An Enhanced 130 nm Generation Logic Technology Featuring 60 nrn Transistors Optimized for High Performance and Low Power at 0.7-1.4V", S. THOMPSON et al., IEEE International Electron Devices Meeting, 2001.
10. Intel@ Pentium@ 4 Processor with 512433 L2 Cache on 0.13 Micron Process at 2 GHz, 2.20 GHz, 2.26 GHz, 2.40 GHz, and 2.53 GHz http://developer.inteI.corn May 2002
11. "The Future of Wires", Ron HO, Kenneth W. MAI, and Mark A. HOROWITZ, Proceedings of the IEEE, April 2001.