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Volumn 2, Issue 1-2, 2006, Pages 73-85

Dynamically configurable security for SRAM FPGA bitstreams

Author keywords

bitstream encryption; design security; field programmable gate arrays; partial reconfiguration and self reconfiguration; reconfigurable architecture

Indexed keywords


EID: 84886597473     PISSN: 17411068     EISSN: 17411076     Source Type: Journal    
DOI: 10.1504/ijes.2006.010166     Document Type: Article
Times cited : (28)

References (34)
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    • A versatile framework for FPGA field updates: an application of partial self-reconfiguration
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    • Gaj, K.1    Chodowiec, P.2
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    • Real-time configuration code decompression for dynamic FPGA self-reconfiguration
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.